Z85C3010PSG Zilog, Z85C3010PSG Datasheet - Page 88

• Manufacturer Part Number: Z85C3010PSG
• Description: IC 10MHZ Z8500 CMOS SCC 40-DIP
• Manufacturer: Zilog
• Series: SCCr

Specifications of Z85C3010PSG

• Processor Type: Z80
• Features: Error Detection and Multiprotocol Support
• Speed: 10MHz
• Voltage: 5V
• Mounting Type: Through Hole
• Package / Case: 40-DIP (0.620", 15.75mm)
• Cpu Speed: 8MHz
• Digital Ic Case Style: DIP
• No. Of Pins: 40
• Supply Voltage Range: 5V
• Operating Temperature Range: 0°C To +70°C
• Svhc: No SVHC (18-Jun-2010)
• Base Number: 85
• Rohs Compliant: Yes
• Clock Frequency: 10MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-3934; Z85C3010PSG

UM010901-0601
Either of two CRC polynomials are used in Synchronous
modes, selected by bit D2 in WR5. If this bit is set to 1, the
CRC-16 polynomial is used, if this bit is set to 0, the CRC-
CCITT polynomial is used. This bit controls the polynomial
selection for both the receiver and transmitter.
The initial state of the generator and checker is controlled
by bit D7 of WR10. When this bit is set to 1, both the gen-
erator and checker have initial values of all ones; if this bit
is set to 0, the initial values are all 0. The SCC presets the
checker whenever the receiver is in Hunt mode so a CRC
reset command is not necessary. However, there is a Re-
set CRC Checker command in WR0. This command is en-
coded in bits D7 and D6 of WR0. If the CRC is used, the
CRC checker is enabled by setting bit D0 of WR3 to 1.
Sync characters can be stripped from the data stream any
time before the first non-sync character is received. If the
sync strip feature is not being used, the CRC is not en-
abled until after the first data character has been trans-
ferred to the receive data FIFO. As previously mentioned,
8-bit sync characters stripped from the data stream are au-
tomatically excluded from CRC calculation.
Change from Five to Eight
Change from Eight to Five
Figure 4-8. Changing Character Length
Time
13
21
29
34
39
8
Some synchronous protocols require that certain charac-
ters be excluded from CRC calculation. This is possible in
the SCC because CRC calculations are enabled and dis-
abled on the fly. To give the processor sufficient time to de-
cide whether or not a particular character should be includ-
ed in the CRC calculation, the SCC contains an 8-bit time
delay between the receive shift register and the CRC
checker. The logic also guarantees that the calculation
only starts or stops on a character boundary by delaying
the enable or disable until the next character is loaded into
the receive data FIFO. Because the nature of the protocol
requires that CRC calculation disable/enable be selected
before the next character gets loaded into the Receive
FIFO, users cannot take advantage of the FIFO.
To understand how this works refer to Figure 4-9 and the
following explanation. Consider a case where the SCC
receives a sequence of eight bytes, called A, B, C, D, E, F,
G and H, with A received first. Now suppose that A is the
sync character, the CRC is calculated on B, C, E, and F,
and that F is the last byte of this message. This process is
used to control the SCC.
12
20
28
33
38
7
Receive Data Buffer
11 10 9
19 18 17 16 15 14
27 26 25 24 23 22
32 31 30 29 28 27
37 36 35 34 33 32
6
5
4
3
8
2
7
SCC™/ESCC™ User’s Manual
1
6
Data Communication Modes
5 Bits
8 Bits
8 Bits
5 Bits
5 Bits
4-13
4