Z85C3010PSG Zilog, Z85C3010PSG Datasheet - Page 66

• Manufacturer Part Number: Z85C3010PSG
• Description: IC 10MHZ Z8500 CMOS SCC 40-DIP
• Manufacturer: Zilog
• Series: SCCr

Specifications of Z85C3010PSG

• Processor Type: Z80
• Features: Error Detection and Multiprotocol Support
• Speed: 10MHz
• Voltage: 5V
• Mounting Type: Through Hole
• Package / Case: 40-DIP (0.620", 15.75mm)
• Cpu Speed: 8MHz
• Digital Ic Case Style: DIP
• No. Of Pins: 40
• Supply Voltage Range: 5V
• Operating Temperature Range: 0°C To +70°C
• Svhc: No SVHC (18-Jun-2010)
• Base Number: 85
• Rohs Compliant: Yes
• Clock Frequency: 10MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-3934; Z85C3010PSG

UM010901-0601
NRZ (Non-Return to Zero). In NRZ, encoding a 1 is rep-
resented by a High level and a 0 is represented by a Low
level. In this encoding method, only a minimal amount of
clocking information is available in the data stream in the
form of transitions on bit-cell boundaries. In an arbitrary
data pattern, this may not be sufficient to generate a clock
for the data from the data itself.
NRZI (Non-Return to Zero Inverted). In NRZI, encoding
a 1 is represented by no change in the level and a 0 is rep-
resented by a change in the level. As in NRZ, only a mini-
mal amount of clocking information is available in the data
stream, in the form of transitions on bit cell boundaries. In
an arbitrary data pattern this may not be sufficient to gen-
erate a clock for the data from the data itself. In the case
of SDLC, where the number of consecutive 1s in the data
stream is limited, a minimum number of transitions to gen-
erate a clock are guaranteed.
ESCC:
TxD Pin Forced High in SDLC feature. When the ESCC
is programmed for SDLC mode with NRZI data encod-
ing and mark idle (WR10 D6=0, D5=1, D3=1), the TxD
pin is automatically forced high when the transmitter
goes to the mark idle state. There are several different
ways for the transmitter to go into the idle state. In
each of the following cases the TxD pin is forced high
when the mark idle condition is reached: data, CRC,
flag and idle; data, flag and idle; data, abort (on under-
run) and idle; data, abort (command) and idle; idle flag
and command to idle mark. The Force High feature is
disabled when the mark idle bit is reset. The TxD pin is
forced High on the falling edge of the TxC cycle after
the falling edge of the last bit of the closing flag. Using
SDLC Loop mode is independent of this feature.
This feature is used in combination with the automatic
SDLC opening flag transmission feature, WR7' D0=1,
to assure that data packets are properly formatted.
Therefore, when these features are used together, it is
not necessary for the CPU to issue any commands
when using the force idle mode in combination with
NRZI data encoding. If WR7' D0 is reset, like the SCC,
it is necessary to reset the mark idle bit (WR10 D2) to
enable flag transmission before an SDLC packet is
transmitted.
FM1 (Bi-phase Mark). In FM1 encoding, also known as bi-
phase mark, a transition is present on every bit cell bound-
ary, and an additional transition may be present in the mid-
dle of the bit cell. In FM1, a 0 is sent as no transition in the
center of the bit cell and a 1 is sent as a transition in the
center of the bit cell. FM1 encoded data contains sufficient
information to recover a clock from the data.
FM0 (Bi-phase Space). In FM0 encoding, also known as
bi-phase space, a transition is present on every bit cell
boundary and an additional transition may be present in
the middle of the bit cell. In FM0, a 1 is sent as no transition
in the center of the bit cell and a 0 is sent as a transition in
the center of the bit cell. FM0 encoded data contains suffi-
cient information to recover a clock from the data.
Manchester (Bi-phase Level). Manchester (bi-phase lev-
el) encoding always produces a transition at the center of
the bit cell. If the transition is Low to High, the bit is 0. If the
transition is High to Low, the bit is 1. Encoding of Manches-
ter format requires an external circuit consisting of a ‘D’
flip-flop and four gates (Figure 3-4). The SCC is used to
decode Manchester data by using the DPLL in the FM
mode and programming the receiver for NRZ data (See
Section 3.1.3).
Data Encoding Initialization. The data encoding method is
selected in the initialization procedure before the transmitter
and receiver are enabled, but no other restrictions apply.
Note that in NRZ and NRZI, the receiver samples the data
only on one edge, as shown in Figure 3-3. However, in FM1
and FM0, the receiver samples the data on both edges.
Also, as shown in Figure 3-3, the transmitter defines bit cell
boundaries by one edge in all cases and uses the other
edge in FM1 and FM0 to create the mid-bit transition.
SCC/ESCC Ancillary Support Circuitry
SCC™/ESCC™ User’s Manual
3-5
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