Z85C3010PSG Zilog, Z85C3010PSG Datasheet - Page 68

• Manufacturer Part Number: Z85C3010PSG
• Description: IC 10MHZ Z8500 CMOS SCC 40-DIP
• Manufacturer: Zilog
• Series: SCCr

Specifications of Z85C3010PSG

• Processor Type: Z80
• Features: Error Detection and Multiprotocol Support
• Speed: 10MHz
• Voltage: 5V
• Mounting Type: Through Hole
• Package / Case: 40-DIP (0.620", 15.75mm)
• Cpu Speed: 8MHz
• Digital Ic Case Style: DIP
• No. Of Pins: 40
• Supply Voltage Range: 5V
• Operating Temperature Range: 0°C To +70°C
• Svhc: No SVHC (18-Jun-2010)
• Base Number: 85
• Rohs Compliant: Yes
• Clock Frequency: 10MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-3934; Z85C3010PSG

UM010901-0601
3.4 DPLL DIGITAL PHASE-LOCKED LOOP
Each channel of the SCC contains a digital phase-locked
loop that can be used to recover clock information from a
data stream with NRZI, FM, NRZ, or Manchester encod-
ing. The DPLL is driven by a clock nominally at 32 (NRZI)
or 16 (FM) times the data rate. The DPLL uses this clock,
along with the data stream, to construct a receive clock for
the data. This clock can then be used as the SCC receive
clock, the transmit clock, or both.
The clock source for the DPLL is selected issuing one of
the two commands in WR14, that is:
The first command selects the baud rate generator as the
clock source. The other command selects the /RTxC pin
as the clock source, independent of whether the /RTxC pin
is a simple input or part of the crystal oscillator circuit.
Initialization of the DPLL is done at any time during the ini-
tialization sequence, but should be done after the clock
modes have been selected in WR11, and before the re-
ceiver and transmitter are enabled. When initializing the
DPLL, the clock source should be selected first, followed
by the selection of the operating mode.
To avoid metastable problems in the counter, the clock
source selection is made only while DPLL is disabled,
since arbitrarily narrow pulses are generated at the output
of the multiplexer when it changes status.
The DPLL is programmed to operate in one of two modes,
as selected by commands in WR14.
Note: A channel or hardware reset disables the DPLL, se-
lects the /RTxC pin as the clock source for the DPLL, and
places it in the NRZI mode.
WR14 (7-5) = 100 selects the BRG
WR14 (7-5) = 101 selects the /RTxC pin
WR14 (7-5) = 111 selects NRZI mode
WR14 (7-5) = 110 selects FM mode
RxD
Edge Detector
Figure 3-5. Digital Phase-Locked Loop
Count Modifier
5-Bit Counter
Figure 3-5 shows a block diagram of the digital phase-
locked loop. It consists of a 5-bit counter, an edge detector,
and a pair of output decoders. The clock for the DPLL
comes from the output of a two-input multiplexer, and the
two outputs go to the transmitter and receive clock
multiplexers. The DPLL is controlled by seven commands
encoded in WR14 bits D7, D6 and D5.
As in the case of the clock source selection, the mode of
operation is only changed while the DPLL is disabled to
prevent unpredictable results.
In the NRZI mode, the DPLL clock must be 32 times the
data rate. In this mode, the transmit and receive clock out-
puts of the DPLL are identical, and the clocks are phased
so that the receiver samples the data in the middle of the
bit cell. In NRZI mode, the DPLL does not require a transi-
tion in every bit cell, so this mode is useful for recovering
the clocking information from NRZ and NRZI data streams.
In the FM mode, the DPLL clock must be 16 times the data
rate. In this mode, the transmit clock output of the DPLL
lags the receive clock outputs by 90 degrees to make the
transmit and receive bit cell boundaries the same, be-
cause the receiver must sample FM data at one-quarter
and three-quarters bit time.
The DPLL is enabled by issuing the Enter Search Mode
command in WR14; that is WR14 (7-5) = 001. The Enter
Search Mode command unlocks the counter, which is held
while the DPLL is disabled, and enables the edge detector.
If the DPLL is already enabled when this command is is-
sued, the DPLL also enters Search Mode.
SCC/ESCC Ancillary Support Circuitry
SCC™/ESCC™ User’s Manual
Decode
Decode
Receive
Clock
Transmit
Clock
3-7
3