Z85C3010PSG Zilog, Z85C3010PSG Datasheet - Page 6

• Manufacturer Part Number: Z85C3010PSG
• Description: IC 10MHZ Z8500 CMOS SCC 40-DIP
• Manufacturer: Zilog
• Series: SCCr

Specifications of Z85C3010PSG

• Processor Type: Z80
• Features: Error Detection and Multiprotocol Support
• Speed: 10MHz
• Voltage: 5V
• Mounting Type: Through Hole
• Package / Case: 40-DIP (0.620", 15.75mm)
• Cpu Speed: 8MHz
• Digital Ic Case Style: DIP
• No. Of Pins: 40
• Supply Voltage Range: 5V
• Operating Temperature Range: 0°C To +70°C
• Svhc: No SVHC (18-Jun-2010)
• Base Number: 85
• Rohs Compliant: Yes
• Clock Frequency: 10MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-3934; Z85C3010PSG

UM010901-0601
Chapter 1
Figure 1-1.
Figure 1-2.
Figure 1-3.
Figure 1-4.
Figure 1-5.
Figure 1-6.
Figure 1-7.
Chapter 2
Figure 2-1.
Figure 2-2.
Figure 2-3.
Figure 2-4.
Figure 2-5.
Figure 2-6.
Figure 2-7.
Figure 2-8a.
Figure 2-8b.
Figure 2-9.
Figure 2-10.
Figure 2-11.
Figure 2-12.
Figure 2-13.
Figure 2-14.
Figure 2-15.
Figure 2-16.
Figure 2-17.
Figure 2-18.
Figure 2-19.
Figure 2-20.
Figure 2-21.
Figure 2-22.
Figure 2-23.
Figure 2-24.
Figure 2-25.
Figure 2-26.
SCC Block Diagram .............................................................................................................................. 1-4
Z85X30 Pin Functions .......................................................................................................................... 1-5
Z80X30 Pin Functions .......................................................................................................................... 1-6
Z85X30 DIP Pin Assignments .............................................................................................................. 1-6
Z85X30 PLCC Pin Assignments ........................................................................................................... 1-6
Z80X30 DIP Pin Assignments .............................................................................................................. 1-7
Z80X30 PLCC Pin Assignments ........................................................................................................... 1-7
Z80X30 Read Cycle ............................................................................................................................. 2-2
Z80X30 Write Cycle .............................................................................................................................. 2-3
Z80X30 Interrupt Acknowledge Cycle .................................................................................................. 2-4
Write Register 7 Prime (WR7') ............................................................................................................. 2-8
Z85X30 Read Cycle Timing ................................................................................................................ 2-10
Z85X30 Write Cycle Timing ................................................................................................................ 2-11
Z85X30 Interrupt Acknowledge Cycle Timing .................................................................................... 2-11
Write Register 7 Prime (WR7') for the 85230 ..................................................................................... 2-14
Write Register 7 Prime for the 85C30 ................................................................................................. 2-14
ESCC Interrupt Sources ..................................................................................................................... 2-16
Peripheral Interrupt Structure ............................................................................................................. 2-17
Internal Priority Resolution ................................................................................................................. 2-17
RR3 Interrupt Pending Bits ................................................................................................................. 2-18
Interrupt Flow Chart (for each interrupt source). ................................................................................ 2-20
Write Register 1 Receive Interrupt Mode Control ............................................................................... 2-22
Special Conditions Interrupt Service Flow .......................................................................................... 2-24
Transmit Interrupt Status When WR7' D5=1 For ESCC ..................................................................... 2-26
Transmit Buffer Empty Bit Status For ESCC For Both WR7' and WR7' D5=0 ................................... 2-27
Transmit Interrupt Status When WR7' D5=0 For ESCC ..................................................................... 2-27
TxIP Latching on the ESCC ................................................................................................................ 2-27
Operation of TBE, Tx Underrun/EOM and TxIP on NMOS/CMOS. .................................................... 2-28
Operation of TBE, Tx Underrun/EOM and TxIP on ESCC ................................................................. 2-29
Flowchart example of processing an end of packet ........................................................................... 2-30
RR0 External/Status Interrupt Operation ............................................................................................ 2-31
Wait On Transmit Timing .................................................................................................................... 2-34
Wait On Transmit Timing .................................................................................................................... 2-34
Wait On Receive Timing ..................................................................................................................... 2-35
iv
SCC™/ESCC™ U
L
IST OF
F
IGURES
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ANUAL