Z85C3010PSG Zilog, Z85C3010PSG Datasheet - Page 54

• Manufacturer Part Number: Z85C3010PSG
• Description: IC 10MHZ Z8500 CMOS SCC 40-DIP
• Manufacturer: Zilog
• Series: SCCr

Specifications of Z85C3010PSG

• Processor Type: Z80
• Features: Error Detection and Multiprotocol Support
• Speed: 10MHz
• Voltage: 5V
• Mounting Type: Through Hole
• Package / Case: 40-DIP (0.620", 15.75mm)
• Cpu Speed: 8MHz
• Digital Ic Case Style: DIP
• No. Of Pins: 40
• Supply Voltage Range: 5V
• Operating Temperature Range: 0°C To +70°C
• Svhc: No SVHC (18-Jun-2010)
• Base Number: 85
• Rohs Compliant: Yes
• Clock Frequency: 10MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-3934; Z85C3010PSG

2.5.1.2 Wait On Receive
The Wait On Receive function is selected by setting D6 or
WR1 to 0, D5 of WR1 to 1, and then enabling the function
by setting D7 of WR1 to 1. In this mode, the /W//REQ pin
carries the /WAIT signal, and is open-drain when inactive
This allows the use of a block move instruction to trans-
fer the receive data. In the case of the Z80X30, /WAIT
goes active in response to /DS going active, but only if
RR8 is being accessed and a read is attempted. In all
other cases, /WAIT remains open-drain. In the case of
the Z85X30, /WAIT goes active in response to /RD go-
ing active, but only if the receive data FIFO is being ac-
cessed, either directly or via the pointers. The /WAIT pin
UM010901-06
01
/RTxC
/WAIT
PCLK
(from Rx FIFO)
Rx Character
/DS or /RD
1
Available
/W//REQ
(=WAIT)
2
FIFO Empty
3
Figure 2-26. Wait On Receive Timing
Figure 2-27. Wait On Receive Timing
4
5•••8
and Low when active. When the processor attempts to
read data from the Receive FIFO when it is empty, the
SCC asserts /WAIT until a character has reached the exit
location of the FIFO (Figure 2-26).
is released in response to the falling edge of PCLK. De-
tails of the timing are shown in Figure 2-27.
Care must be taken when this mode is used. The /WAIT
pin stays active as long as the Receive FIFO remains emp-
ty. When the CPU access the SCC, the CPU remains in
the wait state until data gets into the Receive FIFO, freez-
ing the system.
9
10
Character Available
SCC™/ESCC™ User’s Manual
11
ASYNC Modes
Interfacing the SCC/ESCC
12
SYNC Modes
13
2-35
2