Z85C3010PSG Zilog, Z85C3010PSG Datasheet - Page 47

• Manufacturer Part Number: Z85C3010PSG
• Description: IC 10MHZ Z8500 CMOS SCC 40-DIP
• Manufacturer: Zilog
• Series: SCCr

Specifications of Z85C3010PSG

• Processor Type: Z80
• Features: Error Detection and Multiprotocol Support
• Speed: 10MHz
• Voltage: 5V
• Mounting Type: Through Hole
• Package / Case: 40-DIP (0.620", 15.75mm)
• Cpu Speed: 8MHz
• Digital Ic Case Style: DIP
• No. Of Pins: 40
• Supply Voltage Range: 5V
• Operating Temperature Range: 0°C To +70°C
• Svhc: No SVHC (18-Jun-2010)
• Base Number: 85
• Rohs Compliant: Yes
• Clock Frequency: 10MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-3934; Z85C3010PSG

SCC™/ESCC™ User’s Manual
Interfacing the SCC/ESCC
2.4 INTERFACE PROGRAMMING (Continued)
2.4.8.3 Transmit Interrupt and Tx Underrun/EOM bit in
synchronous modes
As described in the section above, the behavior of the
NMOS/CMOS version and the ESCC is slightly different,
particularly at the end of packet sending. On the
NMOS/CMOS version, the data has higher priority over
CRC data; writing data before this interrupt would
terminate the packet illegally. In this case, the CRC byte(s)
are replaced with a Flag or Sync pattern, followed by the
data written. On the ESCC, the CRC has priority over the
2-28
TxIP
TBE (RR0, D2)
Tx Underrun /EOM
Figure 2-20. Operation of TBE, Tx Underrun/EOM and TxIP on NMOS/CMOS.
Indicating CRC get loaded
Last Data -1
TxIP Reset Command
to Clear Interrupt
Last Data
If TxIP Reset Command
NOT Issued
data. That means after the reception of the Underrun/EOM
(End Of Message) interrupt, it accepts the data for the next
packet without collapsing the packet. On the ESCC, if data
was written during the time period described above, the
TBE bit (bit D2 of RR0) will not be set even if the second
TxIP is guaranteed to set when the flag/sync pattern was
loaded into the Transmit Shift Register, as mentioned
above (Figures 2-17 and 18). Hence, on the ESCC, there
is no need to wait for the second TxIP bit to set before
writing data for the next packet and reducing the overhead.
Can not write data
CRC1
Indicating 1st byte of next packet
can be written this time
Reset Tx Underrun/EOM command
CRC2
Flag
UM010901-06
01