Z85C3010PSG Zilog, Z85C3010PSG Datasheet - Page 228

• Manufacturer Part Number: Z85C3010PSG
• Description: IC 10MHZ Z8500 CMOS SCC 40-DIP
• Manufacturer: Zilog
• Series: SCCr

Specifications of Z85C3010PSG

• Processor Type: Z80
• Features: Error Detection and Multiprotocol Support
• Speed: 10MHz
• Voltage: 5V
• Mounting Type: Through Hole
• Package / Case: 40-DIP (0.620", 15.75mm)
• Cpu Speed: 8MHz
• Digital Ic Case Style: DIP
• No. Of Pins: 40
• Supply Voltage Range: 5V
• Operating Temperature Range: 0°C To +70°C
• Svhc: No SVHC (18-Jun-2010)
• Base Number: 85
• Rohs Compliant: Yes
• Clock Frequency: 10MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-3934; Z85C3010PSG

UM010901-0601
INTRODUCTION
Zilog’s SCC (Serial Communication Controller) is a
popular USART (Universal Synchronous/Asynchronous
Receiver/Transmitter) device, used for a wide range of
applications. For instance, Macintosh systems use the
SCC as a standard communication controller device.
There are several different types of devices in the SCC
family. The family consists of the Z8530 NMOS SCC, the
Z85C30 CMOS SCC, the Z85230 ESCC (Enhanced
SCC), Z85233 EMSCC (Mono Enhanced SCC), and
Superintegration devices such as the Z181 ZIO™ and
Z182 ZIP™.
Since the SCC may be used in many different ways, it may
not be easy to understand all the transactions involved
between the CPU and the SCC. In particular, the SDLC
mode of operation is highly complicated, and many
transactions are involved to make it work properly. This
application note describes the sequence of events which
occurs in the SDLC mode of operation.
The following sequences of events are covered:
U
S
SDLC Transmission
SDLC receive
–
–
–
ERIAL
With Receive Interrupts on all received characters
or Special Conditions
With Receive Interrupts on First Character or
Special Condition
With Receive Interrupts on Special Conditions
only
operating in the SDLC mode simplifies working in this complex area.
nderstanding the transactions which occur within a Serial Communication Controller
C
OMMUNICATION
SDLC M
ODE OF
A
Each section explains the transmit/receive process for
packets with the following characteristics:
Note:
This application note describes the SCC, but not the
ESCC. The ESCC, since it incorporates enhancements
like deeper FIFOs and SDLC mode supporting logic,
handles the packets much more simply than the SCC.
Refer to the section on CMOS SCC and ESCC of this
appnote for more general information on the ESCC.
C
PPLICATION
O
Receiving Back-to-back Frame under DMA control
SDLC Loop mode
Initial state is mark idle
Address field has 81H
Control field has 42H
Two bytes of I-field, 42H and 0FFH
After the closing flag, mark idling
ONTROLLER
PERATION
N
OTE
(SCC
™
):
6-93
10
1