Z85C3010PSG Zilog, Z85C3010PSG Datasheet - Page 117

• Manufacturer Part Number: Z85C3010PSG
• Description: IC 10MHZ Z8500 CMOS SCC 40-DIP
• Manufacturer: Zilog
• Series: SCCr

Specifications of Z85C3010PSG

• Processor Type: Z80
• Features: Error Detection and Multiprotocol Support
• Speed: 10MHz
• Voltage: 5V
• Mounting Type: Through Hole
• Package / Case: 40-DIP (0.620", 15.75mm)
• Cpu Speed: 8MHz
• Digital Ic Case Style: DIP
• No. Of Pins: 40
• Supply Voltage Range: 5V
• Operating Temperature Range: 0°C To +70°C
• Svhc: No SVHC (18-Jun-2010)
• Base Number: 85
• Rohs Compliant: Yes
• Clock Frequency: 10MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-3934; Z85C3010PSG

SCC™/ESCC™ User’s Manual
Register Descriptions
5.1 INTRODUCTION (Continued)
Bits 6 and 5: Transmit Bits/Character select bits
1 and 0
These bits control the number of bits in each byte trans-
ferred to the transmit buffer. Bits sent must be right justified
with the least significant bits first.
The Five Or Less mode allows transmission of one to five
bits per character. For five or fewer bits per character, the
data character must be formatted as shown below in Table
5-5. In the Six or Seven Bits/Character modes, unused
data bits are ignored.
Bit 4: Send Break control bit
When set, this bit forces the TxD output to send continuous
0s beginning with the following transmit clock, regardless
of any data being transmitted at the time. This bit functions
whether or not the transmitter is enabled. When reset, TxD
continues to send the contents of the Transmit Shift regis-
ter, which might be syncs, data, or all 1s. If this bit is set
while in the X21 mode (Monosync and Loop mode select-
ed) and character synchronization is achieved in the re-
ceiver, this bit is automatically reset and the transmitter be-
gins sending syncs or data. This bit is also reset by a
channel or hardware reset.
Note: For five or less bits per character selection in WR5, the fol-
lowing encoding is used in the data sent to the transmitter. D is
the data bit(s) to be sent.
Bit 3: Transmit Enable
Data is not transmitted until this bit is set, and the TxD out-
put sends continuous 1s unless Auto Echo mode or SDLC
Loop mode is selected. If this bit is reset after transmission
starts, the transmission of data or sync characters is com-
pleted. If the transmitter is disabled during the transmis-
sion of a CRC character, sync or flag characters are sent
instead of CRC. This bit is reset by a channel or hardware
reset.
5-10
D7 D6 D5 D4 D3 D2 D1
1
1
1
1
0
Bit 7
0
0
1
1
1
1
1
0
0
Table 5-5. Transmit Bits per Character
1
1
0
0
0
D
1
0
0
0
Bit 6
D
D
0
1
0
1
0
0
0
D
D
D
0
0
D
D
D
D
0
5 or less bits/character
7 bits/character
6 bits/character
8 bits/character
D0
D
D
D
D
D
Sends one data bit
Sends two data bits
Sends three data bits
Sends four data bits
Sends five data bits
Bit 2: SDLC/CRC-16 polynomial select bit
This bit selects the CRC polynomial used by both the
transmitter and receiver. When set, the CRC-16 polynomi-
al is used; when reset, the SDLC polynomial is used. The
SDLC/CRC polynomial is selected when SDLC mode is
selected. The CRC generator and checker can be preset
to all 0s or all 1s, depending on the state of the Preset
1/Preset 0 bit in WR10.
Bit 1: Request To Send control bit
This is the control bit for the /RTS pin. When the RTS bit is
set, the /RTS pin goes Low; when reset, /RTS goes High.
When Auto Enable is set in asynchronous mode, the /RTS
pin immediately goes Low when the RTS bit is set. Howev-
er, when the RTS bit is reset, the /RTS pin remains Low
until the transmitter is completely empty and the last stop
bit has left the TxD pin. In synchronous modes, the
/RTS pin directly follows the state of this bit, except in
SDLC mode under specific conditions. In SDLC mode, if
Flag On Underrun bit (WR10, D2) is set, RTS bit in WR5 is
reset, and D2 in WR7' is set. The /RTS pin deasserts au-
tomatically at the last bit of the closing flag triggered by the
rising edge of the Tx clock. This bit is reset by a channel or
hardware reset.
Bit 0: Transmit CRC Enable
This bit determines whether or not the CRC is calculated
on a transmit character. If this bit is set at the time the char-
acter is loaded from the transmit buffer to the Transmit
Shift register, the CRC is calculated on that character. The
CRC is not automatically sent unless this bit is set when
the transmit underrun exists.
5.2.7 Write Register 6 (Sync Characters or
SDLC Address Field)
WR6 is programmed to contain the transmit sync
character in the Monosync mode, or the first byte of a 16-
bit sync character in the External Sync mode. WR6 is not
used in asynchronous modes. In the SDLC modes, it is
programmed to contain the secondary address field used
to compare against the address field of the SDLC Frame.
In SDLC mode, the SCC does not automatically transmit
the station address at the beginning of a response frame.
Bit positions for WR6 are shown in Figure 5-8.
UM010901-0601