Z85C3010PSG Zilog, Z85C3010PSG Datasheet - Page 79

• Manufacturer Part Number: Z85C3010PSG
• Description: IC 10MHZ Z8500 CMOS SCC 40-DIP
• Manufacturer: Zilog
• Series: SCCr

Specifications of Z85C3010PSG

• Processor Type: Z80
• Features: Error Detection and Multiprotocol Support
• Speed: 10MHz
• Voltage: 5V
• Mounting Type: Through Hole
• Package / Case: 40-DIP (0.620", 15.75mm)
• Cpu Speed: 8MHz
• Digital Ic Case Style: DIP
• No. Of Pins: 40
• Supply Voltage Range: 5V
• Operating Temperature Range: 0°C To +70°C
• Svhc: No SVHC (18-Jun-2010)
• Base Number: 85
• Rohs Compliant: Yes
• Clock Frequency: 10MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-3934; Z85C3010PSG

SCC™/ESCC™ User’s Manual
Data Communication Modes
4.2 ASYNCHRONOUS MODE (Continued)
The transmission of a character begins when the line
makes a transition from the 1 state (or MARK condition) to
the 0 state (or SPACE condition). This transition is the ref-
erence by which the character’s bit cell boundaries are de-
fined. Though the transmitter and receiver have no com-
mon clock signal, they must be at the same data rate so
that the receiver can sample the data in the center of the
bit cell.
The SCC also supports Isochronous mode, which is the
same as Asynchronous except that the clock is the same
rate as the data. This mode is selected by selecting
x1 clock mode in WR4 (D7 & D6=0). Using this mode typ-
ically requires that the transmit clock source be transmitted
along with the data, or that the clock be synchronized with
the data.
The character can be broken up into four fields:
Generation and checking of parity is optional and is con-
trolled by WR4 D1 & D0. WR4 bit D0 is used to enable par-
ity. If WR4 bit D1 is set, even parity is selected and if D1 is
reset, odd parity is selected. For even parity, the parity bit
is set/reset so that the data byte plus the parity bit contains
an even number of 1s. For odd parity, the parity bit is
set/reset such that the data byte plus the parity bit contains
an odd number of 1s.
The SCC supports Asynchronous mode with a number of
programmable options including the number of bits per
character, the number of stop bits, the clock factor, modem
interface signals, and break detect and generation.
Asynchronous mode is selected by programming the de-
sired number of stop bits in D3 and D2 of WR4. Program-
ming these two bits with other than 00 places both the re-
ceiver and transmitter in Asynchronous mode. In this
mode, the SCC ignores the state of bits D4, D3, and D2 of
WR3, bits D5 and D4 of WR4, bits D2 and D0 of WR5, all
4-4
Start bit - signals the beginning of a character frame.
Data field - typically 5-8 bits wide.
Parity bit - optional error checking mechanism.
Stop bit(s) - Provides a minimum interval between the
end of one character and the beginning of the next.
of WR6 and WR7, and all of WR10 except D6 and D5. Ig-
nored bits are programmed with 1 or 0 (Table 4-1).
Note: If WR3 D1 is set (enabling the sync character load inhibit
feature), any character matching the value in WR6 is stripped out
of the incoming data stream and not put into the Receive FIFO.
Therefore, as this feature is typically only desired in synchronous
formats, this bit should reset in Asynchronous mode.
4.2.1 Asynchronous Transmit
Asynchronous mode is selected by specifying the number
of stop bits per character in bits D3 and D2 of WR4. The
three options available are one, one-and-a-half, and two
stop bits per character. These two bits select only the num-
ber of stop bits for the transmitter, as the receiver always
checks for one stop bit.
The number of bits per transmitted character is controlled
both by bits D6 and D5 in WR5 and the way the data is for-
matted within the transmit buffer (in the case of the ESCC,
Transmit FIFO). The bits in WR5 allow the option of five,
six, seven, or eight bits per character. In all cases the data
must be right-justified, with the unused bits being ignored
except in the case of five bits per character. When the five
bits per character option is selected, the data may be for-
matted before being written to the transmit buffer. This al-
lows transmission of from one to five bits per character.
The formatting is shown in Table 4-2.
Register
WR3
WR4
WR5
WR6
WR7
WR10
Table 4-1. Write Register Bits Ignored in
D7
x
x
x
Asynchronous Mode
D6
x
x
D5
x
x
x
D4
x
x
x
x
x
D3
x
x
x
x
UM010901-0601
D2
x
x
x
x
x
D1
0
x
x
x
D0
x
x
x
x