Z85C3010PSG Zilog, Z85C3010PSG Datasheet - Page 272

• Manufacturer Part Number: Z85C3010PSG
• Description: IC 10MHZ Z8500 CMOS SCC 40-DIP
• Manufacturer: Zilog
• Series: SCCr

Specifications of Z85C3010PSG

• Processor Type: Z80
• Features: Error Detection and Multiprotocol Support
• Speed: 10MHz
• Voltage: 5V
• Mounting Type: Through Hole
• Package / Case: 40-DIP (0.620", 15.75mm)
• Cpu Speed: 8MHz
• Digital Ic Case Style: DIP
• No. Of Pins: 40
• Supply Voltage Range: 5V
• Operating Temperature Range: 0°C To +70°C
• Svhc: No SVHC (18-Jun-2010)
• Base Number: 85
• Rohs Compliant: Yes
• Clock Frequency: 10MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-3934; Z85C3010PSG

UM010901-0601
The second routine decrements the receiver buffer
address by two to account for the two CRC bytes that are
read from the SCC before the special condition interrupt
occurs. Note that the SCC does not filter these CRC bytes,
nor does it filter the address byte. Everything received after
the leading flags and before the trailing flags appears in
the receive buffer.
One difficulty that arises in LLAP that was not addressed
here is that the receipt of a frame very often creates an
obligation to send a frame back to the sender within the
CONCLUSIONS
The problems of sending the sync pulses, the timing of
transmission packets, and the problems associated with
the reception of packets as defined by LLAP are handled
by the Z80181 and its peripherals. It was demonstrated
that LLAP frames can be transmitted and received by
using the straight forward polling method and by using
interrupt routines. In a much busier environment where the
processor cannot strictly be an LLAP engine, other
Technical Considerations When Implementing LocalTalk Link Access Protocol
interframe gap, which is 200 secs. This difficulty is even
greater than it might appear. The 200
when the frame is received; it ends when the leading flags
and destination address of the response are sent. Start
sending the response soon enough to allow sending two
leading flags (plus a possible leading flag fragment) and
the first data character, and to allow for the 3-bit delay in
the SCC shifter. Therefore, start sending early enough to
transmit 35 bits before the interframe gap expires, or about
70 secs after you receive the frame.
methods such as using DMA in a fully interrupt driven
environment must be used. It was also demonstrated that
severe CPU overhead is used in setting up the sync
pulses, timing out delays, etc., before each LLAP frame. A
modified SCC that transmits and receives special LLAP
frames helps in off loading some of this overhead, hence
freeing the CPU to do other tasks.
Application Note
sec gap starts
6-137
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