Z85C3010PSG Zilog, Z85C3010PSG Datasheet - Page 34

• Manufacturer Part Number: Z85C3010PSG
• Description: IC 10MHZ Z8500 CMOS SCC 40-DIP
• Manufacturer: Zilog
• Series: SCCr

Specifications of Z85C3010PSG

• Processor Type: Z80
• Features: Error Detection and Multiprotocol Support
• Speed: 10MHz
• Voltage: 5V
• Mounting Type: Through Hole
• Package / Case: 40-DIP (0.620", 15.75mm)
• Cpu Speed: 8MHz
• Digital Ic Case Style: DIP
• No. Of Pins: 40
• Supply Voltage Range: 5V
• Operating Temperature Range: 0°C To +70°C
• Svhc: No SVHC (18-Jun-2010)
• Base Number: 85
• Rohs Compliant: Yes
• Clock Frequency: 10MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-3934; Z85C3010PSG

UM010901-0601
2.3.7 Z85X30 Reset
The Z85X30 may be reset by either a hardware or software
reset. Hardware reset occurs when /WR and /RD are both
Low at the same time, which is normally an illegal condi-
tion. As long as both /WR and /RD are Low, the Z85X30
recognizes the reset condition. However, once this condi-
tion is removed, the reset condition is asserted internally
for an additional four to five PCLK cycles. During this time
any attempt to access is ignored.
Notes:
*WR7' is only available on the 85C30 and the ESCC.
2.4 INTERFACE PROGRAMMING
The following subsections explain and illustrate all areas of
interface programming.
2.4.1 I/O Programming Introduction
The SCC can work with three basic forms of I/O opera-
tions: polling, interrupts, and block transfer. All three I/O
types involve register manipulation during initialization and
data transfer. However, the interrupt mode also incorpo-
rates Z-Bus interrupt protocol for a fast and efficient data
transfer.
WR0
WR1
WR2
WR3
WR4
WR5
WR6
WR7
WR7'*
WR9
WR10
WR11
WR12
WR13
WR14
WR15
RR0
RR1
RR3
RR10
X
X
X
X
X
X
X
X
X
7
0
0
0
0
1
0
0
1
0
0
0
X
X
X
X
X
X
X
X
X
X
6
0
0
0
1
0
0
1
1
0
0
X
X
X
X
X
X
X
X
X
X
5
0
1
0
0
0
1
1
0
0
0
Hardware RESET
X
X
X
X
X
X
X
X
4
0
0
0
0
0
0
0
1
1
0
0
0
X
X
X
X
X
X
X
X
3
0
0
0
0
0
0
1
0
1
0
0
0
Table 2-7. Z85X30 Register Reset Value
X
X
X
X
X
X
X
2
0
1
0
0
0
0
0
0
0
1
1
0
0
1
0
0
X
X
X
0
X
X
0
X
0
0
X
X
0
0
0
1
0
0
X
X
X
X
X
X
X
X
X
0
0
0
0
0
0
0
0
0
0
0
0
The Z85X30 has three software resets that are encoded
into the command bits in WR9. There are two channel re-
sets which only affect one channel in the device and
some bits of the write registers. The command forces the
same result as the hardware reset, the Z85X30 stretches
the reset signal an additional four to five PCLK cycles be-
yond the ordinary valid access recovery time. The bits in
WR9 may be written at the same time as the reset com-
mand because these bits are affected only by a hardware
reset. The reset values of the various registers are shown
in Table 2-7.
Regardless of the version of the SCC, all communication
modes can use a choice of polling, interrupt and block
transfer. These modes are selected by the user to deter-
mine the proper hardware and software required to supply
data at the rate required.
Note to ESCC Users: Those familiar with the NMOS/CMOS
version will find the ESCC I/O operations very similar but
should note the following differences: the addition of soft-
ware acknowledge (which is available in the current version
of the CMOS SCC, but not in NMOS); the /DTR//REQ pin
can be programmed to be deasserted faster; and the pro-
grammability of the data interrupts to the FIFO fill level.
X
X
X
X
X
X
X
X
X
X
X
7
0
0
0
0
0
1
0
0
0
X
X
X
X
X
X
X
X
X
X
X
X
X
6
0
0
0
1
1
0
0
X
X
X
X
X
X
X
X
X
X
X
X
5
0
1
0
1
1
0
0
0
Channel RESET
SCC™/ESCC™ User’s Manual
X
X
X
X
X
X
X
X
X
X
4
0
0
0
0
0
0
1
0
0
0
Interfacing the SCC/ESCC
X
X
X
X
X
X
X
X
X
X
3
0
0
0
0
0
0
1
0
0
0
2
0
X
X
X
1
0
X
X
0
X
0
X
X
X
0
0
1
1
0
0
X
X
X
X
X
X
X
X
X
X
1
0
0
0
0
0
0
0
1
0
0
2-15
X
X
X
X
X
X
X
X
X
X
X
0
0
0
0
0
0
0
0
0
0
2