Z85C3010PSG Zilog, Z85C3010PSG Datasheet - Page 91

• Manufacturer Part Number: Z85C3010PSG
• Description: IC 10MHZ Z8500 CMOS SCC 40-DIP
• Manufacturer: Zilog
• Series: SCCr

Specifications of Z85C3010PSG

• Processor Type: Z80
• Features: Error Detection and Multiprotocol Support
• Speed: 10MHz
• Voltage: 5V
• Mounting Type: Through Hole
• Package / Case: 40-DIP (0.620", 15.75mm)
• Cpu Speed: 8MHz
• Digital Ic Case Style: DIP
• No. Of Pins: 40
• Supply Voltage Range: 5V
• Operating Temperature Range: 0°C To +70°C
• Svhc: No SVHC (18-Jun-2010)
• Base Number: 85
• Rohs Compliant: Yes
• Clock Frequency: 10MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-3934; Z85C3010PSG

SCC™/ESCC™ User’s Manual
Data Communication Modes
4.3 BYTE-ORIENTED SYNCHRONOUS MODE (Continued)
4-16
Stage
Legend:
* Usually D is a end-of-message character indicator.
† The status is latched on the Error FIFO for each received byte. In the calculation of F,
the CRC error flag in the Error FIFO will be 0 for an error free message.
d = disabled
e = enabled
A B C D E F G H
A = SYNC
B - F = Data with E = CRC1 and F = CRC2
G and H are arbitrary data (Pad Character)
1
2
3
4
5
(Sync)
Note: No CRC Calculation on "D"
A
(Data1)
Coming into SCC
CPU Reads & Disca
Direction of Data
B
CPU Disables CR
CPU Enables CR
CPU Enables CR
Read H & Disca
H G F E D C B
Read RR1 D
(Data2)
H G F E D C
H G F E D C
CPU Read
CPU Read
CPU Read
CPU Read
CPU Read
C
H G F E D
H G F E
H G F
H G
(Data3)
H
D
Table 4-7. Enabling and Disabling CRC
Register
(CRC1)
Shift
E
A
C
D
E
H
B
G
F
(CRC2)
F
Data FIFO
Receive
D*
B
C
E
G
F
H
H
(Data)
G
Register
(Data)
Delay
H
C
D
E
B
G
F
CRC
d
d
d
e
e
d
e
e
e
CRC Calc on B
CRC Calc on C
CRC Calc is
Disabled on D
CRC Calc on E
CRC Calc on F
CRC Calc on F
Result latched in
Error FIFO †
Notes
UM010901-0601