Z85C3010PSG Zilog, Z85C3010PSG Datasheet - Page 57

• Manufacturer Part Number: Z85C3010PSG
• Description: IC 10MHZ Z8500 CMOS SCC 40-DIP
• Manufacturer: Zilog
• Series: SCCr

Specifications of Z85C3010PSG

• Processor Type: Z80
• Features: Error Detection and Multiprotocol Support
• Speed: 10MHz
• Voltage: 5V
• Mounting Type: Through Hole
• Package / Case: 40-DIP (0.620", 15.75mm)
• Cpu Speed: 8MHz
• Digital Ic Case Style: DIP
• No. Of Pins: 40
• Supply Voltage Range: 5V
• Operating Temperature Range: 0°C To +70°C
• Svhc: No SVHC (18-Jun-2010)
• Base Number: 85
• Rohs Compliant: Yes
• Clock Frequency: 10MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-3934; Z85C3010PSG

SCC™/ESCC™ User’s Manual
Interfacing the SCC/ESCC
2.5 BLOCK/DMA TRANSFER (Continued)
2.5.2.3 DMA Request On Transmit (using /DTR//REQ)
A second Request on Transmit function is available on the
/DTR//REQ pin. This mode is selected by setting D2 of
WR14 to 1. /REQ goes Low when the Transmit FIFO is
empty if WR7' D5=1, or when the exit location of the Trans-
mit FIFO is empty if WR7' D5=0. In the Request mode,
/REQ follows the state of the Transmit FIFO even though
ESCC:
The timing of deactivation of this pin is programmable
through WR7' bit D4. The /DTR//REQ waits until the
write operation has been completed before going in-
active. Refer to Z85230 AC spec #35a TdWRr(REQ)
and Z80230 AC spec #27a TdDSr(REQ). This mode is
compatible with the SCC and guarantees that any sub-
sequent access to the ESCC does not violate the valid
access recovery time requirement.
If WR7' D4=1, the /DTR//REQ is deactivated with iden-
tical timing as the /W/REQ pin. Refer to Z85230 AC
2-38
/WAIT//REQ
/DS or /WR
/DTR//REQ
D7-D0
Figure 2-31. /DTR//REQ Deassertion Timing
Transmit Data
ESCC WR7' D4 =1
ESCC WR7' D4 =0, or CMOS/NMOS version
the transmitter is disabled. While D2 of WR14 is set to 0,
the /DTR//REQ pin is /DTR and follows the inverted state
of D7 in WR5. This pin is High after a channel or hardware
reset and in the DTR mode.
The /DTR//REQ pin goes inactive High between each
transfer for a minimum of one PCLK cycle (Figure 2-31).
spec #35b TdWRr(REQ) and Z80230 AC spec #27b
TdDSr(REQ). This feature is beneficial to applications
needing the DMA request to be deasserted quickly. It
prevents a full Transmit FIFO from being overwritten
due to the assertion of REQUEST being too long and
being recognized as a request for more data.
Note: If WR7' D4=1, analysis should be done to verify
that the ESCC is not repeatedly accessed in less than
four PCLKs. However, since many DMAs require four
clock cycles to transfer data, this typically is not a
problem.
UM010901-06
01