Z85C3010PSG Zilog, Z85C3010PSG Datasheet - Page 214

• Manufacturer Part Number: Z85C3010PSG
• Description: IC 10MHZ Z8500 CMOS SCC 40-DIP
• Manufacturer: Zilog
• Series: SCCr

Specifications of Z85C3010PSG

• Processor Type: Z80
• Features: Error Detection and Multiprotocol Support
• Speed: 10MHz
• Voltage: 5V
• Mounting Type: Through Hole
• Package / Case: 40-DIP (0.620", 15.75mm)
• Cpu Speed: 8MHz
• Digital Ic Case Style: DIP
• No. Of Pins: 40
• Supply Voltage Range: 5V
• Operating Temperature Range: 0°C To +70°C
• Svhc: No SVHC (18-Jun-2010)
• Base Number: 85
• Rohs Compliant: Yes
• Clock Frequency: 10MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-3934; Z85C3010PSG

UM010901-0601
INTRODUCTION
Zilog’s Z8030 Z-SCC Serial Communications Controller is
one of a family of components that are Z-BUS
with the Z8000™ CPU. Combined with a Z8000 CPU (or
other existing 8- or 16-bit CPUs with nonmultiplexed buses
when using the Z8530 SCC), the Z-SCC forms an
integrated data communications controller that is more
cost
incorporating UARTs, baud rate generators, and phase-
locked loops as separate entities.
The approach examined here implements a communications
controller in a Binary Synchronous mode of operation, with a
Z8002 CPU acting as controller for the Z-SCC.
DATA TRANSFER MODES
The Z-SCC system interface supports the following data
transfer modes:
Polled Mode. The CPU periodically polls the Z-SCC
status registers to determine the availability of a
received character, if a character is needed for
transmission, and if any errors have been detected.
Interrupt Mode. The Z-SCC interrupts the CPU when
certain previously defined conditions are met.
effective
and
S
more
YNCHRONOUS
compact
SCC
than
®
compatible
systems
IN
C
B
OMMUNICATIONS
A
One channel of the Z-SCC is used to communicate with
the remote station in Half Duplex mode at 9600
bits/second.
Development Modules are used. Both are loaded with the
same
transmitting and receiving messages. The main program
of one module requests the transmit routine to send a
message of the length indicated in the ‘COUNT’
parameter. The other system receives the incoming data
stream, storing the message in its resident memory.
The example given here uses the block mode of data
transfer in its transmit and receive routines.
PPLICATION
INARY
Block/DMA Mode. Using the Wait/Request (/W//REQ)
signal, the Z-SCC introduces extra wait cycles to
synchronize data transfer between a CPU or DMA
controller and the Z-SCC.
software
To
N
routines
test
OTE
this
for
application,
initialization
two
and
Z8000
6-79
for
9
9