Z85C3010PSG Zilog, Z85C3010PSG Datasheet - Page 182
![IC 10MHZ Z8500 CMOS SCC 40-DIP](/photos/6/57/65796/269-40-dip_sml.jpg)
Z85C3010PSG
Manufacturer Part Number
Z85C3010PSG
Description
IC 10MHZ Z8500 CMOS SCC 40-DIP
Manufacturer
Zilog
Series
SCCr
Specifications of Z85C3010PSG
Processor Type
Z80
Features
Error Detection and Multiprotocol Support
Speed
10MHz
Voltage
5V
Mounting Type
Through Hole
Package / Case
40-DIP (0.620", 15.75mm)
Cpu Speed
8MHz
Digital Ic Case Style
DIP
No. Of Pins
40
Supply Voltage Range
5V
Operating Temperature Range
0°C To +70°C
Svhc
No SVHC (18-Jun-2010)
Base Number
85
Rohs Compliant
Yes
Clock Frequency
10MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
269-3934
Z85C3010PSG
Z85C3010PSG
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
Z85C3010PSG
Manufacturer:
Zilog
Quantity:
135
Company:
Part Number:
Z85C3010PSG
Manufacturer:
Zilog
Quantity:
326
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UM010901-0601
;*
;*
;*
;*
.z800
*include 180macro.lib
;SCC
Registers
scc_ad:
scc_ac:
scc_bd:
scc_bc:
scc_a:
scc_cont:
scc_cont:
org
inttest:
wait_loop:
wait_here:
;subroutine to initialize scc registers
;initialization table format is
;register number, then followed by the data to be written
;and the register number is 0ffh, then return
initscc:
init0:
Table 12. SCC Test Program – Interrupt for 180/SCC Application Board (Under Mode2 Interrupt)
B register returns status info:
Bit D0: current /cts stat
D1set: /cts int received
if
else
endif
09000h
;Read in Z180 register names and
;macro for Z180 new instructions
equ
equ
equ
equ
equ
scc_a
equ
equ
;top of user ram area
ld
ld
ld
im
call
ld
ei
bit
jr
jr
ld
ld
cp
ret
out
inc
ld
out
inc
jr
0C3h
0C2h
0C1h
0C0h
000h
scc_ac
scc_bc
sp,top_of_sp
a,high sccvect and 0ffh
i,a
2
initscc
b,0
1,b
z,wait_loop
$
hl,scctab
a,(hl)
0ffh
z
(scc_cont),a
hl
a,(hl)
(scc_cont),a
hl
init0
The Z180™ Interfaced with the SCC at MHZ
;addr of scc ch a - data
;addr of scc ch a - control
;addr of scc ch b - data
;addr of scc ch b - control
;set 0ffh to test ch a
;clear 00h to test ch b.
;init sp
;init i reg
;set interrupt mode 2
;initialize scc
;clear status
;enable interrupt
;check int status
;if not, loop again
;interrupt has been received
;you can set breakpoint here!
;initialize scc
;get register number
;reached at the end of table?
;yes, return.
;write it
;point to next data
;get the data to be written
;write it
;point to next data
;then loop
Application Note
6-47
7
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