Z85C3010PSG Zilog, Z85C3010PSG Datasheet - Page 48

• Manufacturer Part Number: Z85C3010PSG
• Description: IC 10MHZ Z8500 CMOS SCC 40-DIP
• Manufacturer: Zilog
• Series: SCCr

Specifications of Z85C3010PSG

• Processor Type: Z80
• Features: Error Detection and Multiprotocol Support
• Speed: 10MHz
• Voltage: 5V
• Mounting Type: Through Hole
• Package / Case: 40-DIP (0.620", 15.75mm)
• Cpu Speed: 8MHz
• Digital Ic Case Style: DIP
• No. Of Pins: 40
• Supply Voltage Range: 5V
• Operating Temperature Range: 0°C To +70°C
• Svhc: No SVHC (18-Jun-2010)
• Base Number: 85
• Rohs Compliant: Yes
• Clock Frequency: 10MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-3934; Z85C3010PSG

An example flowchart for processing an end of packet is
shown in Figure 2-22. The chart includes the differences in
processing between the ESCC and NMOS/CMOS version.
In this chart, Tx IP and Underrun/EOM INT can be
processed by interrupts or by polling the registers. Note
UM010901-06
01
TBE
Tx Underrun /EOM
TxIP
Indicating CRC get loaded
Figure 2-21. Operation of TBE, Tx Underrun/EOM and TxIP on ESCC
Last Data -1
TxIP Reset Command
to Clear Tx Interrupt
Last Data
If TxIP Reset Command
NOT Issued
Data can be written to Tx FIFO after this point
that this flowchart does not have the procedures for
interrupt handling, such as saving/restoring of registers to
be used in the ISR (Interrupt Service Routine), Reset IUS
command, or return from interrupt sequence.
CRC1
Reset Tx Underrun/EOM Latch Command
When Auto EOM Reset has enabled
CRC2
Set if Tx FIFO is Empty
SCC™/ESCC™ User’s Manual
Interfacing the SCC/ESCC
Flag
2-29
2