Z85C3010PSG Zilog, Z85C3010PSG Datasheet - Page 315

• Manufacturer Part Number: Z85C3010PSG
• Description: IC 10MHZ Z8500 CMOS SCC 40-DIP
• Manufacturer: Zilog
• Series: SCCr

Specifications of Z85C3010PSG

• Processor Type: Z80
• Features: Error Detection and Multiprotocol Support
• Speed: 10MHz
• Voltage: 5V
• Mounting Type: Through Hole
• Package / Case: 40-DIP (0.620", 15.75mm)
• Cpu Speed: 8MHz
• Digital Ic Case Style: DIP
• No. Of Pins: 40
• Supply Voltage Range: 5V
• Operating Temperature Range: 0°C To +70°C
• Svhc: No SVHC (18-Jun-2010)
• Base Number: 85
• Rohs Compliant: Yes
• Clock Frequency: 10MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-3934; Z85C3010PSG

SCC™/ESCC™ User’s Manual
Zilog SCC
MISCELLANEOUS QUESTIONS
Q. Can the SCC support MARK and SPACE parity in
A. The SCC can transmit-end the equivalent of MARK par-
The SCC (and products using the SCC cell) does notsup-
Q. Since both D7 and D1 bits in RR0 are not latched,
A. Very few people actually use the Zero Count interrupt.
Q. Can the SCC resynchronize independent clocks
A. No, the two clocks are independent of each other.
7-10
occurred when in fact, an Abort condition oc-
curred and was missed. What could be done to
correct this and not miss the fact that an Abort oc-
curred?
async?
ity by setting WR4 to select two STOP bits. The receiv-
er always checks for only one STOP bit; therefore, the
receiver does not verify the MARK parity bit.
port SPAC parity for transmitting or receiving. The
Zilog USC Family of serial datacom controllers do sup-
port odd, even, mark, & space parity types.
it is possible that the receiver detected an Abort
condition, set D7 to 1, initiated an external/status
interrupt and before the processor entered the ser-
vice routine, termination of the abort was detect-
ed, which reset the Break Abort bit . Currently in
the TM (page 7-20), the description for Bit1: Zero
Count states if the interrupt service routine does
not see any changes in the External/Status condi-
tions, it should assume that a zero count transition
This interrupt is generated TWICE during each bit time
and is usually used to count a specific number of bits
that are sent or received. If this interrupt is not used by
your customer, then what is said in the TM about the
Zero Count is true for the Abort Condition. If no other
changes occurred in the external/status conditions
and the Zero Count is not used, then the source of the
interrupt was the Abort condition.
(at the same frequency, but could be out of phase),
one for Rx data and one for Tx data?
However, the SCC provides a special transmitter-to-
receiver synchronization function that may be used to
guarantee that the character boundaries for the re-
ceived and transmitted data are the same.
Q. When is EOM and EOF asserted?
A. EOM is asserted when it detects depletion of data in
Q. After powering up the SCC, are the reset values in
A. No. You must perform a hardware or software reset.
Q. Can you read the status of a write register, such as
A. No, in order to retain the status of a write register, you
Q. Is there a signal to indicate that a closing SDLC
A. No, the only way to find this timing is to count the num-
Q. Does the SCC detect a loss of the receive clock
A. No, if the clock stops, the SCC senses that the bit time
Q. Is there any harm in grounding the “NO CON-
A. These NC pins are not physically connected inside the
Q. Can the SCC be used as a shift register in one of
A. CRC is optional in Mono-, Bi-, and External Sync
the Tx buffer; EOF is asserted when it detects a clos-
ing flag.
the write and read registers guaranteed?
the MIE bit in WR9?
must keep its status in a separate memory for later
use. However, the only exception is that WR15 is a
mirror image of RR15. Also, the ESCC has a new fea-
ture to allow the user to read some of the write regis-
ters (see the ESCC Product Specification or Technical
Manual for more details).
flag is completely shifted out of the TxD pin? This
is needed to indicate that the frame is completely
free of the output to allow carrier cut off without
disrupting the CRC or closing flag.
ber of clocks from Tx Underrun Interrupt to the closing
flag. The ESCC contains the feature by deasserting
the /RTS pin after the closing flag. Upgrade to the ES-
CC!
signal?
is very long. Use a watch-dog timer to detect a loss in
the receive clock signal.
NECT” (NC) pins in the PLCC package (pin
#17,18,28,36)?
die. Therefore, it is safe to tie them to ground.
the synchronous modes with only data sent to the
Tx register with no CRC and no sync characters?
Modes only. The sync characters can be stripped out
via software.
UM010901-0601