Z85C3010PSG Zilog, Z85C3010PSG Datasheet - Page 62

• Manufacturer Part Number: Z85C3010PSG
• Description: IC 10MHZ Z8500 CMOS SCC 40-DIP
• Manufacturer: Zilog
• Series: SCCr

Specifications of Z85C3010PSG

• Processor Type: Z80
• Features: Error Detection and Multiprotocol Support
• Speed: 10MHz
• Voltage: 5V
• Mounting Type: Through Hole
• Package / Case: 40-DIP (0.620", 15.75mm)
• Cpu Speed: 8MHz
• Digital Ic Case Style: DIP
• No. Of Pins: 40
• Supply Voltage Range: 5V
• Operating Temperature Range: 0°C To +70°C
• Svhc: No SVHC (18-Jun-2010)
• Base Number: 85
• Rohs Compliant: Yes
• Clock Frequency: 10MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-3934; Z85C3010PSG

UM010901-0601
3.1 INTRODUCTION
The serial channels of the SCC are supported by ancillary
circuitry for generating clocks and performing data encod-
ing and decoding. This chapter presents a description of
these functional blocks.
Note to ESCC/CMOS Users: The maximum input fre-
quency to the DPLL has been specified as two times the
PCLK frequency (Spec #16b TxRX(DPLL)). There are no
changes to the baud rate generators from the NMOS to the
CMOS/ESCC.
3.2 BAUD RATE GENERATOR
The Baud Rate Generator (BRG) is essential for
asynchronous communications. Each channel in the SCC
contains a programmable baud rate generator. Each
generator consists of two 8-bit, time-constant registers
forming a16-bit time constant, a 16-bit down counter, and
a flip-flop on the output so that it outputs a square wave.
On start-up, the flip-flop on the output is set High, so that it
starts in a known state, the value in the time-constant
/RTxC Pin
PCLK Pin
WR 13
16-Bit Counter
Figure 3-1. Baud Rate Generator
Baud Rate
Generator
Clock
(Takes One More
Clock to Load
Time Constant
Value to
Counter
WR12
U
C
SCC/ESCC A
S
Note to SCC Users: The ancillary circuitry in the ESCC is
the same as in the SCC with the following noted changes.
The DPLL (Dual Phased-Locked Loop) output, when used
as the transmit clock source, has been changed to be free
of jitter. Consequently, this only affects the use of the DPLL
as the transmit clock source (it is typically used for the re-
ceive clock source), this has no effect on using the DPLL
as the receive clock source.
register is loaded into the counter, and the counter begins
counting down. When a count of zero is reached, the
output of the baud rate generator toggles, the value in the
time-constant register is loaded into the counter, and the
process starts over. The programmed time constant is
read from RR12 and RR13. A block diagram of the baud
rate generator is shown in Figure 3-1.
SER
UPPORT
2
HAPTER
’
Mode
Clock
S
M
Zero
Count
Output
ANUAL
C
IRCUITRY
(Gives one Transition
Each Time the Counter
Counts to Zero)
(May Provide
Higher Resolution
to Sample Data)
Desired Baud
(Asynchronous Mode)
NCILLARY
3
3-1
3