Z85C3010PSG Zilog, Z85C3010PSG Datasheet - Page 52

• Manufacturer Part Number: Z85C3010PSG
• Description: IC 10MHZ Z8500 CMOS SCC 40-DIP
• Manufacturer: Zilog
• Series: SCCr

Specifications of Z85C3010PSG

• Processor Type: Z80
• Features: Error Detection and Multiprotocol Support
• Speed: 10MHz
• Voltage: 5V
• Mounting Type: Through Hole
• Package / Case: 40-DIP (0.620", 15.75mm)
• Cpu Speed: 8MHz
• Digital Ic Case Style: DIP
• No. Of Pins: 40
• Supply Voltage Range: 5V
• Operating Temperature Range: 0°C To +70°C
• Svhc: No SVHC (18-Jun-2010)
• Base Number: 85
• Rohs Compliant: Yes
• Clock Frequency: 10MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-3934; Z85C3010PSG

UM010901-06
01
crystal option in External Sync mode is illegal, but the re-
sult will be the same.
In Synchronous modes other than SDLC, the Sync/Hunt
reports the Hunt state of the receiver. Hunt mode is en-
tered when the processor issues the Enter Hunt command
in WR3. This forces the receiver to search for a sync char-
acter match in the receive data stream. Because both tran-
sitions of the Hunt bit close the latches, issuing this com-
mand will cause an External/Status interrupt. The SCC
resets this bit when character synchronization has been
achieved, causing the latches to again be closed.
In these synchronous modes, the SCC will not re-enter the
Hunt mode automatically; only the Enter Hunt command will
set this bit. In SDLC mode this bit is also set by the Enter
Hunt command, but the receiver automatically enters the
Hunt mode if an Abort sequence is received. The receiver
leaves Hunt upon receipt of a flag sequence. Both transi-
tions of the Hunt bit will cause the latches to be closed. In
2.5 BLOCK/DMA TRANSFER
The SCC provides a Block Transfer mode to accommo-
date CPU block transfer functions and DMA controllers.
The Block Transfer mode uses the /W//REQ output in con-
junction with the Wait/Request bits in Write Register 1. The
/W//REQ output can be defined by software as a /WAIT
line in the CPU Block Transfer mode or as a /REQ line in
the DMA Block Transfer mode. The /DTR//REQ pin can
also be programmed through WR14 bit D2 to function as a
DMA request for the transmitter.
To a DMA controller, the SCC's /REQ outputs indicate that
the SCC is ready to transfer data to or from memory. To
the CPU, the /WAIT output indicates that the SCC is not
ready to transfer data, thereby requesting the CPU to ex-
tend the I/O cycle.
2.5.1 Block Transfers
The SCC offers several alternatives for the block transfer
of data. The various options are selected by WR1 (bits D7
through D5) and WR14 (bit D2). Each channel in the SCC
SDLC mode, the receiver automatically synchronizes on
Flag characters. The receiver is in Hunt mode when it is en-
abled, so the Enter Hunt command is never needed.
2.4.9.6 External/Status Interrupt Handling
If careful attention is paid to details, the interrupt service
routine for External/Status interrupts is straightforward. To
determine which bit or bits changed state, the routine
should first read RR0 and compare it to a copy from mem-
ory. For each changed bit, the appropriate action should
be taken and the copy in memory updated. The service
routine should close with two Reset External/Status inter-
rupt commands to reopen the latches. The copy of RR0 in
memory should always have the Zero Count bit set to 0,
since this is the state of the bit after the Reset Exter-
nal/Status interrupts command at the end of the service
routine. When the processor issues the Reset Transmit
Underrun/EOM latch command in WR0, the Transmit Un-
derrun/EOM bit in the copy of RR0 in memory should be
reset because this transition does not cause an interrupt.
has two pins which are used to control the block transfer of
data. Both pins in each channel may be programmed to act
as DMA Request signals. The /W//REQ pin in each chan-
nel may be programmed to act as a Wait signal for the
CPU. In either mode, it is advisable to select and enable
the mode in two separate accesses of the appropriate reg-
ister. The first access should select the mode and the sec-
ond access should enable the function. This procedure
prevents glitches on the output pins. Reset forces Wait
mode, with /W//REQ open-drain.
2.5.1.1 Wait On Transmit
The Wait On Transmit function is selected by setting both
D6 and D5 to 0 and then enabling the function by setting
D7 of WR1 to 1. In this mode the /W//REQ pin carries the
/WAIT signal, and is open-drain when inactive and Low
when active. When the processor attempts to write to the
transmit buffer when it is full, the SCC asserts /WAIT until
the byte is written (Figure 2-24).
SCC™/ESCC™ User’s Manual
Interfacing the SCC/ESCC
2-33
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