Z85C3010PSG Zilog, Z85C3010PSG Datasheet - Page 75
Z85C3010PSG
Manufacturer Part Number
Z85C3010PSG
Description
IC 10MHZ Z8500 CMOS SCC 40-DIP
Manufacturer
Zilog
Series
SCCr
Specifications of Z85C3010PSG
Processor Type
Z80
Features
Error Detection and Multiprotocol Support
Speed
10MHz
Voltage
5V
Mounting Type
Through Hole
Package / Case
40-DIP (0.620", 15.75mm)
Cpu Speed
8MHz
Digital Ic Case Style
DIP
No. Of Pins
40
Supply Voltage Range
5V
Operating Temperature Range
0°C To +70°C
Svhc
No SVHC (18-Jun-2010)
Base Number
85
Rohs Compliant
Yes
Clock Frequency
10MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
269-3934
Z85C3010PSG
Z85C3010PSG
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SCC™/ESCC™ User’s Manual
SCC/ESCC Ancillary Support Circuitry
3.6 CRYSTAL OSCILLATOR (Continued)
Figure 3-13 shows the use of the DPLL to derive a 1x clock
from the data. In this example:
The DPLL clock input = BRG output (x16 the data rate)
WR14.
3.6 CRYSTAL OSCILLATOR
Each channel contains a high gain oscillator amplifier for
use with an external crystal circuit. The amplifier is avail-
able between the /RTxC pin (crystal input) and the /SYNC
pin (crystal output) for each channel.
The oscillator amplifier is enabled by writing WR11 D7=1.
While the crystal oscillator is enabled, anything that has
selected the /RTxC pin as its clock source automatically
connects to the output of the crystal oscillator.
Note: The output of the oscillator amplifier can be pro-
grammed to output on the /TRxC pin, which is particularly
valuable for diagnostic purposes. Because amplifier char-
acteristics can be affected by the impedance of measure-
ment equipment applied directly to the crystal circuit, using
the /TRxC pin allows the oscillation to be tested without af-
fecting the circuit.
3-14
Figure 3-13. Synchronous Transmission, 1x Clock Rate, FM Data Encoding, using DPLL
External
Crystal
RxD Pin
/SYNC Pin
/RTxC Pin
The DPLL clock output = RxC (receiver clock) WR11.
Set FM mode WR14.
Set FM mode WR10.
Of course, since the oscillator uses the /RTxC and /SYNC
pins, this precludes the use of these pins for other func-
tions. In synchronous modes, no sync pulse is output, and
the External Sync mode cannot be selected. In asynchro-
nous modes, the state of the Sync/Hunt bit in RR0 is no
longer controlled by the /SYNC pin. Instead, the Sync/Hunt
bit is forced to 0.
The crystal oscillator requires some finite time to stabilize
and must be allowed to stabilize before it is used as a clock
source. This stabilization time is dependent on the external
circuit impedance and 20 ms is a suggested minimum. The
External Crystal should operate in parallel resonance. For
further details on designing with the crystal, refer to Appen-
dix A, “On-Chip Oscillator Design”.
G
B
R
D
P
L
L
16x Data Rate
RxD
RxC
TxC
UM010901-0601
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