Z85C3010PSG Zilog, Z85C3010PSG Datasheet - Page 53

• Manufacturer Part Number: Z85C3010PSG
• Description: IC 10MHZ Z8500 CMOS SCC 40-DIP
• Manufacturer: Zilog
• Series: SCCr

Specifications of Z85C3010PSG

• Processor Type: Z80
• Features: Error Detection and Multiprotocol Support
• Speed: 10MHz
• Voltage: 5V
• Mounting Type: Through Hole
• Package / Case: 40-DIP (0.620", 15.75mm)
• Cpu Speed: 8MHz
• Digital Ic Case Style: DIP
• No. Of Pins: 40
• Supply Voltage Range: 5V
• Operating Temperature Range: 0°C To +70°C
• Svhc: No SVHC (18-Jun-2010)
• Base Number: 85
• Rohs Compliant: Yes
• Clock Frequency: 10MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-3934; Z85C3010PSG

SCC™/ESCC™ User’s Manual
Interfacing the SCC/ESCC
2.5 BLOCK/DMA TRANSFER (Continued)
This allows the use of a block move instruction to transfer
the transmit data. In the case of the Z80X30, /WAIT will go
active in response to /DS going active, but only if WR8 is
being accessed and a write is attempted. In all other cas-
es, /WAIT remains open-drain. In the case of the Z85X30,
/WAIT goes active in response to /WR going active, but
only if the data buffer is being accessed, either directly or
via the pointers. The /WAIT pin is released in response to
2-34
/TRxC
/WAIT
PCLK
Tx Buffer Empty
to Tx Buffer
/DS or /WR
/W//REQ
(=WAIT)
Figure 2-25. Wait On Transmit Timing
Figure 2-24. Wait On Transmit Timing
Full
the falling edge of PCLK. Details of the timing are shown
in Figure 2-25.
Care must be taken when using this function, particularly
at slow transmission speed. The /WAIT pin stays active as
long as the transmit buffer stays full, so there is a possibil-
ity that the CPU may be kept waiting for a long period.
Empty
ASYNC Modes
SYNC Modes
UM010901-06
01