TXC-04222-AIOG Transwitch Corporation, TXC-04222-AIOG Datasheet - Page 10

• Manufacturer Part Number: TXC-04222-AIOG
• Manufacturer: Transwitch Corporation

Specifications of TXC-04222-AIOG

• Screening Level: Industrial
• Package Type: BGA
• Lead Free Status / Rohs Status: Not Compliant

June 2003
TEMx28
TXC-04222
TXC-04222-MB, Ed. 6
BLOCK DIAGRAM DESCRIPTION
As illustrated in Figure 1, the TEMx28 interfaces to four buses, designated as A Drop, B Drop, A Add, and B
Add. The four buses run at the STM-1/STS-3 rate of 19.44 Mbyte/s. For North American applications,
asynchronous DS1 signals are carried in a floating Virtual Tributary 1.5 (VT1.5) format, while E1 signals are
carried in a floating Virtual Tributary 2 (VT2) format. A maximum of 28 VT1.5 and 21 VT2 signals are carried in
a Synchronous Transport Signal - 1 (STS-1) format. Three STS-1s are in turn carried in a STS-3 signal. For
ITU-T applications, asynchronous E1 signals are carried in floating mode Tributary Unit - 12 (TU-12) format and
DS1 signals are carried in floating mode Tributary Unit - 11 (TU-11) format. The TU-12s and TU-11s are carried
in an STM-1 Virtual Container - 4 (VC-4) structure using Tributary Unit Group - 3 (TUG-3), or in the STM-1
Virtual Container - 3 (VC-3) structure using Tributary Unit Group - 2 (TUG-2) mapping schemes. Up to 28 DS1
or E1 signals, or a combination of DS1 and E1 signals, can be dropped from one bus (A Drop or B Drop) to the
DS1 or E1 lines. A maximum of 28 asynchronous DS1 or E1 signals are converted into TU-11/TU-12 or
VT1.5/VT2 format and are added to either of the add buses, or both, depending upon the mode of operation.
The TEMx28 can provide, on a per channel basis, the Virtual Container - 11 (VC-11), or the E1 Virtual Container
- 12 (VC-12) formats in place of the DS1 or E1 signals for Virtual Concatenation applications. The VC format
contains the payload and overhead bytes associated with the TU-11 and TU-12 formats.
The TEMx28 also supports the cross mapping feature specified in ITU Recommendation G707. This feature
enables a DS1 asynchronous line signal to be carried in a TU-12/VT2 payload. This feature is supported in the
TEMx28 on a per channel basis.
When the TEMx28 is configured for drop bus timing, the add buses are, by definition, byte- and
multiframe-synchronous with their like-named drop buses, but are delayed by one or two byte times because of
internal processing. For example, if a byte in the STM-1 Virtual Container - 4 (VC-4) structure using Tributary
Unit Group - 3 (TUG-3), TU-12/VT2 is to be added to the A Add bus, the time of its placement on the bus is
derived from the A Drop bus timing, and from software instructions specifying which TU/VT number is being
added. Note that the TU/VT A drop bus selection can be different from the A add bus selection. An option is
provided which enables the dropped timing signals to be sent as outputs on the add bus. When the device is
configured for add bus timing, the add bus, parity, and add indicator signals are derived from the input add bus
clock, C1J1V1 and SPE signals.
In the drop (receive) direction, the A Receive Drop Bus Interface block is identical to the B Receive block. The
TU/VT Terminate block, Destuff block and Desychronizer block are repeated 56 times, 28 for each side (A and
B sides). The Channel n Receive Interface blocks are repeated 28 times, one for each channel. The interface
between a drop bus and the receive block consists of 12 input leads: a 19.44 MHz byte clock, byte-wide data,
a C1J1 indicator which may be also carrying a V1 indication making the signal a C1J1V1 indicator, an SPE
indicator, and an odd/even parity bit. The Drop C1J1V1 signal is used in conjunction with the Drop SPE signal
to determine the location of the various bytes in the SONET/SDH format. A single J1 pulse identifies the
starting location of the J1 byte in the VC-4 format, when the SPE signal is high. Three J1 pulses are provided
for the STS-3 format, each identifying the starting location of the J1 byte in each of the three STS-1 signals.
The TEMx28 can function with either a V1 pulse in the C1J1V1 signal, or it can use an internal H4 detector, for
determining the location of the V1 byte. The V1 pulse location is used to determine the location of the pointer
bytes V1 and V2. For STM-1 VC-4 operation, if the C1J1V1 signal is used, a one add or drop bus clock cycle
wide pulse must occur every four frames and three drop bus clock cycles after the J1 pulse while the SPE is
high. The J1 pulse identifies the J1 byte location (defined as the starting location for the VC-4) in the POH
bytes. In the next column (first clock cycle) all the rows are assigned as fixed stuff. Similarly, in the next column
(second clock cycle) all the rows are assigned as fixed stuff. The next column (third clock cycle) defines the
start of TUG-3 A. This column is where the V1 pulse occurs every four frames. However, the actual V1 byte
location is six clock cycles after the V1 pulse. For STS-3 operation, three V1 pulses must be present every four
frames. Each of the three V1 pulses must be present three clock cycles after the corresponding J1 pulse, when
the SPE signal is high.
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