TXC-04222-AIOG Transwitch Corporation, TXC-04222-AIOG Datasheet - Page 22

• Manufacturer Part Number: TXC-04222-AIOG
• Manufacturer: Transwitch Corporation

Specifications of TXC-04222-AIOG

• Screening Level: Industrial
• Package Type: BGA
• Lead Free Status / Rohs Status: Not Compliant

June 2003
TEMx28
TXC-04222
TXC-04222-MB, Ed. 6
BAC1J1(V1)
CHANNEL n LINE INTERFACE (n = 1, up to 28)
(n=1-28)
(n=1-28)
Symbol
RVTCn
RVTDn
Symbol
RCLKn
RDATn
RCOn
RPOn
BADD
V20, W22, T21,
V22, R20, N19,
C21, A21, C17,
D15, B15, C13,
Y18, Y21, U19,
P20, M19, L21,
J22, G22, G20,
E21, E19, D18,
B18, C16, A16,
A14, B12, D11,
C9, B7, A4, C5
N22, L20, J21,
J19, F21, C22,
A12, B10, A8,
AA13, AB15,
AA16, AB19,
AA19, AA21,
Lead No. I/O/P
AB17, W16,
A6, D7, B4
W12, Y14,
Lead No.
M3
L2
Proprietary TranSwitch Corporation Information for use Solely by its Customers
I/O(T) TTL3V/
O
I/O/P
O(T)
O(T)
CMOS3V
CMOS3V
Type
8mA
8mA
CMOS3V
CMOS3V
Type
4mA
4mA
DATA SHEET
B Add Bus C1J1V1 Indications: An active high timing signal that
carries STM-1/STS-3 frame and SPE information. This signal works
in conjunction with the AASPE signal. The C1 pulse identifies the
location of the first C1 byte in the STM-1 and STS-3 signals, when
AASPE signal is low. The J1 pulse identifies the starting location of
the J1 byte in the STM-1 VC-4 signal when ADSPE is high. Three J1
pulses identify the starting location for each of the three STS-1 sig-
nals in the STS-3 signal. A single V1 pulse identifies the starting
location for the V1/V2 bytes in the TUG-3 within the VC-4. Three V1
pulses identify the starting location of the V1/V2 bytes within each of
the three STS-1s. When drop bus timing is selected (lead ABUST is
high), and lead ABTE is low, this signal, which is derived from the
like-named drop bus is an output. When lead ABTE is high in the
B drop bus timing mode, this lead is disabled and forced to the high
impedance state.
B Add Bus Add Data Present Indicator: This normally active low
signal is present when output data to the A Add bus is valid. It identi-
fies the location of all of the TU/VT time slots being selected. When
control bit ADDI (bit 0, register 03AH) is 1, the indicator is active high
instead of active low.
Receive Channel n Rail, NRZ, TU/VT Output Clock: A DS1,
E1, or VT/TU clock output. Data (Rail or NRZ) is clocked out on
positive transitions of this clock when control bit RnCLKI (bit 3,
register X+000H) is a 1. When control bit RnCLKI is a 0, data is
clocked out on negative transitions of this clock. RCOn is the
E1/T1 rail clock (control bits RnLINT1/0 (bits 7/6, register
X+006H) are 10). RCLKn is the NRZ clock (control bits
RnLINT1/0 are 01). RVTCn is the TU/VT NRZ clock (control
bits RnLINT1/0 are 11). This lead is disabled when control bits
RnLINT1/0 are 00. When disabled, this lead can be forced to
ether a high impedance state (control bit RnOUTL (bit 5, regis-
ter 006H) is a 0), or to zeros (control bit RnOUTL is a 1). Lead
AA13 is RCO1/RCLK1/RVTC1 (Channel 1).
Note: See Description for control bit RnOUTL for detailed operation.
Receive Channel n Data Positive Rail, NRZ, TU/VT: When
control bits RnLINT1/0 are set to 10, positive rail E1/T1 data
(RPOn) is provided on this lead. When control bit RnLINT1/0 is
set to 01, NRZ E1/T1 data (RDATn) is provided on this lead.
When control bits RnLINT1/0 are set to 11, VT/TU NRZ data
(RVTDn) is provided on this lead. This lead is disabled when
control bits RnLINT1/0 are 00. When disabled, this lead can be
forced to ether a high impedance state (control bit RnOUTL is a
0), or to zeros (control bit RnOUTL is a 1). Lead W12 is
RPO1/RDAT1/RVTD1 (Channel 1).
Note: See Description for control bit RnOUTL for detailed operation.
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Name/Function
Name/Function