TXC-04222-AIOG Transwitch Corporation, TXC-04222-AIOG Datasheet - Page 20

• Manufacturer Part Number: TXC-04222-AIOG
• Manufacturer: Transwitch Corporation

Specifications of TXC-04222-AIOG

• Screening Level: Industrial
• Package Type: BGA
• Lead Free Status / Rohs Status: Not Compliant

June 2003
TEMx28
TXC-04222
TXC-04222-MB, Ed. 6
B DROP AND B ADD BUS I/O
AAC1J1(V1)
Symbol
BD(7-0)
BDCLK
BDPAR
BDSPE
Symbol
AADD
Lead No. I/O/P
Lead No. I/O/P
C2, D2,
D3, B1,
E4, E3,
C1, F4
G4
D1
F3
R1
R3
Proprietary TranSwitch Corporation Information for use Solely by its Customers
I/O(T)
O
I
I
I
I
CMOS3V
CMOS3V
TTL3V B Drop Bus Clock: This clock operates at 19.44 MHz for
TTL3V B Drop Bus Parity Bit: A parity bit input signal representing the odd
TTL3V B Drop Bus Data Byte: Byte-wide data that corresponds to the
TTL3V B Drop Bus SPE Indicator: A signal that is active high for each
TTL3V/
Type *
Type
8mA
8mA
DATA SHEET
STM-1/STS-3 operation. A Drop bus byte-wide data (BD7-BD0), the
parity bit (BDPAR), SPE indication (BDSPE), and the C1J1V1 indi-
cation (BADC1J1V1) are clocked in on falling edges of this clock.
This clock may also be used for add bus timing and deriving the
like-named add bus byte-wide data, add and TU/VT indications, and
parity bits.
or even parity calculation for each data byte, SPE, and C1J1V1 sig-
nal from the drop bus, or the data byte only.
STM-1/STS-3 signal on the drop bus. The first bit received
(dropped) corresponds to bit 7 which is lead D3.
byte of the STM-1 VC-4 and STS-3/STS-1 SPEs, and low for over-
head byte times.
A Add Bus C1J1V1 Indications: An active high timing signal that
carries STM-1/STS-3 frame and SPE information. This signal works
in conjunction with the AASPE signal. The C1 pulse identifies the
location of the first C1 byte in the STM-1 and STS-3 signals, when
AASPE signal is low. The J1 pulse identifies the starting location of
the J1 byte in the STM-1 VC-4 signal when ADSPE is high. Three J1
pulses identify the starting location for each of the three STS-1 sig-
nals in the STS-3 signal. A single V1 pulse identifies the starting
location for the V1/V2 bytes in the TUG-3 within the VC-4. Three V1
pulses identify the starting location of the V1/V2 bytes within each of
the three STS-1s. When drop bus timing is selected (lead ABUST is
high), and lead ABTE is low, this signal, which is derived from the
like-named drop bus is an output. When lead ABTE is high in the
A drop bus timing mode, this lead is disabled.
A Add Bus Add Data Present Indicator: This normally active low
signal is present when output data to the A Add bus is valid. It identi-
fies the location of all of the TU/VT time slots being selected. When
control bit ADDI (bit 0, register 03AH) is 1, the indicator is active high
instead of active low.
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Name/Function
Name/Function