TXC-04222-AIOG Transwitch Corporation, TXC-04222-AIOG Datasheet - Page 42

• Manufacturer Part Number: TXC-04222-AIOG
• Manufacturer: Transwitch Corporation

Specifications of TXC-04222-AIOG

• Screening Level: Industrial
• Package Type: BGA
• Lead Free Status / Rohs Status: Not Compliant

June 2003
TEMx28
TXC-04222
TXC-04222-MB, Ed. 6
Figure 17. STM-1 VC-4 A/B Drop and Add Bus Signals, Timing Derived from Drop Bus (lead ABTE low)
Note: A single TU/VT (number 21/28 in STS-1 number 3) is shown for illustration purposes. The A and B add bus out-
A/BDCLK clock period
A/BDCLK duty cycle t
A/BD(7-0)/A/BDPAR data /parity setup time before A/BDCLK
A/BD(7-0)/A/BDPAR data /parity hold time after A/BDCLK
A/BDSPE setup time before A/BDCLK
A/BDSPE hold time after A/BDCLK
A/BDC1J1V1 setup time before A/BDCLK
A/BDC1J1V1 hold time after A/BDCLK
A/BACLK delay from A/BDCLK
A/BAC1J1V1 delay from A/BACLK
A/BASPE delay from A/BCLK
A/B(7-0) and A/BAPAR data /parity out valid delay from
A/BACLK
A/BADD delay from A/BACLK
Note: All output times are measured with the 50 pf load capacitance.
A/BDC1J1V1
A/BAC1J1V1
A/BD(7-0)
A/BDSPE
A/BA(7-0)
A/BDCLK
A/BDPAR
A/BACLK
A/BASPE
A/BAPAR
A/BADD
(Output)
(Output)
(Output)
(Output)
(Output)
(Input)
(Input)
(Input)
(Input)
puts are delayed an additional clock cycle from their respective drop bus timing inputs when control bit ABOD (bit
1, 03BH) is written with a 1.
t
t
SU(1)
SU(3)
C1(1)
C1(1)
Proprietary TranSwitch Corporation Information for use Solely by its Customers
t
t
H(1)
H(3)
PWH
C1(2)
t
PWH
C1(1)
t
OD(2)
/t
Parameter
CYC
t
CYC
C1(3)
t
SU(2)
t
OD(3)
Data
DATA SHEET
t
H(2)
- 42 of 246 -
t
OD(1)
Selected
TU/VT
STS-1 #1
J1 Byte
Selected
J1
TU/VT
t
t
OD(4)
OD(5)
Symbol
t
t
t
t
t
t
t
t
t
OD(1)
OD(2)
OD(3)
OD(4)
OD(5)
SU(1)
t
SU(2)
t
SU(3)
t
CYC
H(1)
H(2)
H(3)
STS-1 #2
Occurs every four frames
when provided in place
J1
of the H4 byte
STS-1 #3
Min
-2.0
-2.0
-2.0
-2.0
5.0
2.0
5.0
3.0
5.0
3.0
4.0
40
STS-1 #1
Data
51.44
Typ
50
Max
12.0
10.0
2.5
2.5
7.0
60
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
%