TXC-04222-AIOG Transwitch Corporation, TXC-04222-AIOG Datasheet - Page 198

• Manufacturer Part Number: TXC-04222-AIOG
• Manufacturer: Transwitch Corporation

Specifications of TXC-04222-AIOG

• Screening Level: Industrial
• Package Type: BGA
• Lead Free Status / Rohs Status: Not Compliant

June 2003
TEMx28
TXC-04222
TXC-04222-MB, Ed. 6
CHANNEL n - B SIDE DESYNCHRONIZER REGISTER DESCRIPTION (n = 1 to 28)
CHANNEL n - A AND B SIDE ADD BUS ALARM MASK BITS (n = 1 to 28)
Address
Address
X+087
X+088
X+005
7-0
7-2
1-0
7-6
Bit
Bit
5
4
3
2
1
0
Proprietary TranSwitch Corporation Information for use Solely by its Customers
(Bits 9-8)
MnTLOC
MnBTFE
MnTLOS
MnATFE
Symbol
Symbol
(Bit 7-0)
MnTAIS
MnOOL
B Drop
Pointer
B Drop
Pointer
Value
Value
Leak
Rate
Leak
Rate
B Side Drop Bus Channel n Desynchronizer Pointer Leak Rate Reg-
ister Bits 7-0: This register contains the first 8 bits in a 10 bit pointer
leak register. The value written into this location and the next location is
used for the internal leak rate buffer, and represents the average leak
rate based on a count. A count of one represents 8 frames, or 2 multi-
frames, between bits leaked. Bit 0 is the LSB.
Note: If the 10 bit register is set to 0 the pointer leak buffer in the Desyn-
chronizer is bypassed. The following alarms will cause the contents of
locations X+087H and X+088H to be reset to their default values:
BnLOP, BnAIS, B1UAIS, B2UAIS, B3UAIS or B1HLOM, B2HLOM, or
B3HLOM. Following these alarms, 3 rising edges of PM1S are required
before X+087H and X+088H can be written to.
Not used:
B Side Drop Bus Channel n Desynchronizer Pointer Leak Rate Reg-
ister Bits 9-8: This register contains the last two bits in a 10 bit pointer
leak register. The value written into this location along with the register is
used for the internal leak rate buffer, and represents the average leak
rate based on a count. A count of one represents 8 frames, or 2 multi-
frames, between bits leaked. Bit 9 is the MSB.
Note: If the 10 bit register is set to 0 the pointer leak buffer in the Desyn-
chronizer is bypassed.
Not used:
Transmit Channel n Line AIS Alarm Mask Bit: A 1 enables the hard-
ware interrupt for a Line AIS for channel n.
Transmit B Side Add Bus Channel n FIFO Error Indication Mask Bit:
A 1 enables the hardware interrupt for a B side FIFO error indication for
channel n.
Transmit A Side Add Bus Channel n FIFO Error Indication Mask Bit:
A 1 enables the hardware interrupt for a A side FIFO error indication for
channel n.
Channel n Test Analyzer Out Of Lock Alarm Mask Bit: A 1 enables
the hardware interrupt for a test analyzer out of lock alarm for channel n.
Transmit Channel n Loss Of Signal Alarm Mask Bit: A 1 enables the
hardware interrupt for a transmit loss of signal alarm for channel n.
Transmit Channel n Loss Of Clock Alarm mask Bit: A 1 enables the
hardware interrupt for a transmit loss of clock alarm for channel n.
DATA SHEET
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Description
Description