TXC-04222-AIOG Transwitch Corporation, TXC-04222-AIOG Datasheet - Page 11

• Manufacturer Part Number: TXC-04222-AIOG
• Manufacturer: Transwitch Corporation

Specifications of TXC-04222-AIOG

• Screening Level: Industrial
• Package Type: BGA
• Lead Free Status / Rohs Status: Not Compliant

Proprietary TranSwitch Corporation Information for use Solely by its Customers
TEMx28
DATA SHEET
TXC-04222
Each drop bus (A and B) is monitored for parity errors, loss of clock, H4 multiframe alignment if selected, and
an upstream SDH/SONET AIS indication. The TEMx28 can monitor either the TOH E1 order wire bytes or the
H1/H2 bytes for an upstream AIS indication.
Each TU/VT Terminate block (A and B side) performs pointer processing using the V1 and V2 bytes. The
pointer bytes are monitored for loss of pointer, Alarm Indication Signal (AIS), and a New Data Flag (NDF). The
pointer tracking process is based on ETSI/ITU-T standards, which also meets ANSI requirements. Pointer
increments and decrements are also counted, and the size bits are monitored for the correct value. This block
also processes and monitors the various alarms found in the four overhead bytes. These operations including
signal label mismatch detection, unequipped status detection, BIP-2 parity error detection and error counter,
REI error counting, and single-bit or three-bit Remote Defect Indications (RDI). The TEMx28 performs a
16-byte J2 trail trace comparison on the channels selected. For 64-byte messages, the bytes are stored in a
memory map segment for a microprocessor read cycle. The device also provides the TU tandem connection
feature and performs the 16-byte message comparison for the N2 (formerly known as Z6) byte message.
All VT/TU overhead bytes, eight overhead communications channel bits (O-bits), the V1/V2 pointer bytes, and
the V4 byte for each channel are available for a microprocessor read cycle. Also, the E1 order wire bytes, the
H1/H2 pointer bytes, and the H4 bytes from the upstream circuitry are also available for a microprocessor read
cycle.
A control bit for each port selects the TU/VT from either the A Drop or B Drop bus. The TU/VT is destuffed in the
Destuff block using majority logic rules for the three sets of three justification control bits to determine if the two
S-bits are data bits or frequency justification bits.
The Desynchronizer block removes the effects on the DS1 or E1 output of systemic jitter that might occur
because of signal mappings and pointer movements in the network. The Desynchronizer block is comprised of
a pointer leak buffer and a loop buffer. The pointer leak buffer spaces bursts of pointer movements more
gradually over time and can accept up to five consecutive pointer movements. The loop buffer consists of a
digital loop filter, which is designed to track the frequency of the received signal and to remove both
transmission and stuffing jitter.
The Channel n Receive Interface block of each channel provides either NRZ data, positive and negative rail
signal, or a VT/TU interface. Receive data (towards the line), for each of the channels, can be clocked out on
either rising or falling edges of the clock. In addition, a control bit is provided for forcing the data and clock
signals to a high impedance state (tristate), or to the zero state.
In the add (transmit) direction, the TEMx28 accepts a clock and either NRZ data or positive and negative rail
signals. Data, for each of the channels, can be clocked in on either the falling or rising edge of the clock. In the
NRZ mode, an external loss of clock indication or external coding violations can be provided. For the rail signal,
coding violations are counted, and there is a loss of signal detector. A DS1/E1 AIS detector is also provided.
Each channel can also be configured for VT/TU interface for Virtual Concatenation data applications. When this
interface is selected, a clock signal is provided for strobing in data for either the A or B bus. Four framing pulses
are also provided which define the starting location of the VT1.5/TU-11 and VT2/TU-12. An option is provided
for including the four overhead bytes. However, except for bits 1 and 2 in the K4 bytes, the other bits are
ignored. Bits 1 and 2 in the K4 byte carry an extended signal label and information pertaining to the payload
position within the Virtual Concatenation channel. The Virtual Concatenation channel will be assigned to n
VT/TUs based on the data bandwidth required for the application.
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TXC-04222-MB, Ed. 6
June 2003