TXC-04222-AIOG Transwitch Corporation, TXC-04222-AIOG Datasheet - Page 24

• Manufacturer Part Number: TXC-04222-AIOG
• Manufacturer: Transwitch Corporation

Specifications of TXC-04222-AIOG

• Screening Level: Industrial
• Package Type: BGA
• Lead Free Status / Rohs Status: Not Compliant

June 2003
TEMx28
TXC-04222
TXC-04222-MB, Ed. 6
CONTROLS, EXTERNAL CLOCK, FRAMING PULSES AND TEST LEADS
Symbol Lead No. I/O/P
VTFA15
DSCLK
RESET
HIGHZ
VTFA2
PM1S
TEST
ABTE
AB12
U2
U3
Y5
V1
R4
T4
T2
Proprietary TranSwitch Corporation Information for use Solely by its Customers
O
O
I
I
I
I
I
I
CMOS3V
CMOS3V
TTL3Vp TranSwitch Test Lead: This lead is used for TranSwitch testing and
TTL3Vp Hardware Reset: When an active low pulse is applied to this lead for a
TTL3Vp High Impedance Select: A low forces all output leads, except the
TTL3Vp Add Bus Timing Output Signals enable: An active low enables the
TTL3V Desynchronizer Reference Clock: This clock is used for desynchro-
TTL3V One Second Performance Clock Input. This clock input is used for the
4 mA
4 mA
Type
must remain an active high for the mapper to function. This lead is pulled
high by an internal pull-up to VDD2. It must be left floating or held high.
nizer operation and for other internal functions, such as generating a
receive AIS signal. The clock frequency must be 68.68 MHz (+/- 30 ppm
over life) and the clock duty cycle must be (50 +/- 10)%.
minimum duration of 150 nanoseconds after power is applied, this pulse
clears all performance counters and alarms, resets the control bits, and
initializes the internal FIFOs. This action takes approximately 4 micro-
seconds. Status bit RESETD (bit 0, register 059H) is set to 1 when the
reset is complete. This lead is pulled high by an internal pull-up to VDD2.
boundary scan lead TDO, to the high impedance state for testing pur-
poses. This lead is pulled high by an internal pull-up to VDD2.
one second shadow counters, and PM (Performance Monitoring)/FM
(Fault Monitoring) alarm registers. This clock should be a 1.0 Hz +/- 32
ppm clock, with a minimum 30 ns high and low time. When this lead is
held low, the PM/FM alarm and shadow counter features are disabled.
This clock is required to write to the Bit Leak Registers in X+017H and
X+018H.
like-named drop bus clock, C1J1V1 and SPE signals to be provided as
output signals on the add bus when the drop bus timing mode is selected
(lead ABUST is high). When high, the clock, C1J1V1, and SPE signals
are disabled as outputs on the add buses when the drop bus timing
mode is selected. This lead is pulled high by an internal pull-up to VDD2.
Transmit VT1.5 Framing Pulse. Positive one clock cycle pulse that is
used when the VT/TU line interface is selected for a channel. The pulse
determines the start of the VT1.5/TU-11 multiframe in the transmit direction
for Add Bus A. The pulse occurs even when no VT/TU line interface is
selected (as long as Add Bus A is active). The pulse is clocked out on the ris-
ing edge of the TVTCn clock when control bit TnCLKI (bit 3, register X+002H)
is a 0.
Transmit VT2 Framing Pulse. Positive one clock cycle pulse that is used
when the VT/TU line interface is selected for a channel. The pulse deter-
mines the start of the VT2/TU-12 multiframe in the transmit direction for Add
Bus A. The pulse occurs even when no VT/TU line interface is selected (as
long as Add Bus A is active). The pulse is clocked out on the rising edge of
the TVTCn clock when control bit TnCLKI (bit 3, register X+002H) is a 0.
DATA SHEET
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Name/Function