TXC-04222-AIOG Transwitch Corporation, TXC-04222-AIOG Datasheet - Page 195

• Manufacturer Part Number: TXC-04222-AIOG
• Manufacturer: Transwitch Corporation

Specifications of TXC-04222-AIOG

• Screening Level: Industrial
• Package Type: BGA
• Lead Free Status / Rohs Status: Not Compliant

Address
X+0D3
(cont.)
Proprietary TranSwitch Corporation Information for use Solely by its Customers
Bit
4
3
2
BTnTCEN
BnUQGE
BnUQSU
Symbol
B Side Add Bus Channel n Unequipped Channel Generation: This
control bit works in conjunction with the BnUQSU control bit according to
the following table:
BnUQGE BnUQSU
Note: X = don’t care (0 or 1).
B Side Add Bus Channel n Unequipped Supervisory Channel
Enabled: Works in conjunction with the BnUQGE control bit according to
the table given above.
B Side Add Bus Channel n Tandem Connection Enable: Works in con-
junction with the BTnJ2TSZ bit according to the following table:
BTnTCEN BTnJ2TSZ
Note: X = don’t care (0 or 1).
0
1
1
0
1
1
- 195 of 246 -
X
0
1
DATA SHEET
X
0
1
Normal Operation.
Unequipped TU/VT generated. An unequipped
VT/TU consists of a normal NDF, size bits equal
to 10 (VT2/TU-12) or 11 (VT1.5/TU-11), a fixed
pointer equal to 105 (VT2/TU-12) or 78
(VT1.5/TU-11), and all other bytes equal to 00H.
Unequipped supervisory VT/TU generated. An
unequipped supervisory TU/VT consists of a nor-
mal NDF, size bits equal to 10 (VT2/TU-12) or 11
(VT1.5/TU-11), a fixed pointer equal to 105
(VT2/TU-12) or 78 (VT1.5/TU-11), and a valid J2
byte. The V5 byte will consist of a valid BIP-2, sig-
nal label set to 0. The N2 byte will be sent as zero.
The RDI bits, V5 bit 8 and K4 bits 5, 6 and 7 will be
controlled by the microprocessor and the payload
will set to zeros.
Tandem Connection feature is disabled. The
N2 byte transmitted is the microprocessor writ-
ten value at register X+0D1H.
Tandem Connection feature is enabled. The J2
64 byte message RAM segment is used on a
shared basis. The Transmit J2 message and N2
byte are configured for 16-byte message sizes.
The J2 message segment is configured for a 64
message size. The single byte microprocessor
written value is repeated and transmitted 16
times along with the multiframe alignment pat-
tern, and TC ODI and TC RDI.
Action
Description
Action
TXC-04222-MB, Ed. 6
TXC-04222
TEMx28
June 2003