TXC-04222-AIOG Transwitch Corporation, TXC-04222-AIOG Datasheet - Page 86

• Manufacturer Part Number: TXC-04222-AIOG
• Manufacturer: Transwitch Corporation

Specifications of TXC-04222-AIOG

• Screening Level: Industrial
• Package Type: BGA
• Lead Free Status / Rohs Status: Not Compliant

June 2003
TEMx28
TXC-04222
TXC-04222-MB, Ed. 6
TEST FUNCTIONS
PRBS PATTERN GENERATOR AND ANALYZER
Each DS1 or E1 channel has a PRBS generator and analyzer. The PRBS pattern is selectable, either a 2
or 2
T1M1.3/92-006R3. The 2
T1.403-1995 and T1M1.3/92-006R3. When control bit TnPRN (bit 2, X+004H) is a 0, the PRBS pattern is
defined as 2
The test pattern generator is enabled when control bit TnPTG (bit 5, X+004H) is a 1. The analyzer is enabled
when control bit TnANZ (bit 4, X+004H) is a 1. In addition, on a global basis, when control bit PRBSG (bit 1,
018H) is a 0, the generators are configured for the transmit direction and when set to 1, are configured for the
receive direction. When control bit PRBSA (bit 3, 018H) is 0, all analyzers are in the receive direction and when
set to 1 are configured for the transmit direction. Note that when the generators are replaced in the receive
path, a channel must have a VT/TU selected for the generator to operate.
An out of lock alarm (CnOOL (bit 2, X+100H)) is provided when the PRBS analyzer is enabled. An out of lock
alarm occurs when there is a bit mismatch in the analyzed PRBS pattern. Recovery occurs when:
Figure 33 shows the placement of the PRBS generator and analyzer.
BIP-2 Error Generation
For each channel, a BIP-2 error may be transmitted in the V5 byte. When control bit ATnFB2 (bit 3, X+064H) or
BTnFB2 (bit 3, X+0D4H) is set to a 1, the transmitted BIP-2 is transmitted inverted from its calculated value for
one frame. In order to send another error, the control bit must be first written with a 0.
REI Error Generation
For each channel, an REI error may be transmitted in the V5 byte. When control bit ATnFFB (bit 6, X+065H) or
BTnFFB (bit 6, X+0D5H) is set to a 1, the REI value will be transmitted as a 1 once in the next available V5
byte. A pending REI error as a result of a BIP-2 error, shall be queue, until completion of sending the error is
complete. In order to send another error, the control bit must be first written with a 0.
Loopbacks
The TEMx28 supports two loopbacks on the DS1/E1 line side: facility and line loopback on a per channel
basis. Bidirectional loopback occurs when facility and line loopback are simultaneously enabled. It also sup-
ports a COMBUS SONET/SDH loopback. The three loopbacks are illustrated in Figure 33. Note that the facility
and line loopbacks are not supported when the VT/TU line interface is selected.
The selection of the loopbacks is according to the following table:
Facility loopback enables the transmit DS1 or E1 data and clock signals to be looped back as the receive Data
and Clock signals. The transmit data is sent for the VT/TU selected.
• The analyzed data is in lock for the 2
• The analyzed data is in lock for the 2
20
-1 pattern. The 2
(bit 1, X+004H)
15
LnLBK
-1.
0
0
1
1
Proprietary TranSwitch Corporation Information for use Solely by its Customers
20
15
-1s pattern, referred to as a QRS pattern, is unframed and is defined in
-1 pattern is unframed and is defined in Recommendation O.151, and
(bit 0, X+004H)
FnLBK
0
1
0
1
DATA SHEET
15
20
-1 pattern for more then 25 clock cycles.
-1 pattern for more then 32 clock cycles.
Off
Facility Loopback enabled.
Line loopback enabled.
Bidirectional loopback enabled.
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Loopback Selection
15
-1