TXC-04222-AIOG Transwitch Corporation, TXC-04222-AIOG Datasheet - Page 26

• Manufacturer Part Number: TXC-04222-AIOG
• Manufacturer: Transwitch Corporation

Specifications of TXC-04222-AIOG

• Screening Level: Industrial
• Package Type: BGA
• Lead Free Status / Rohs Status: Not Compliant

June 2003
TEMx28
TXC-04222
TXC-04222-MB, Ed. 6
BOUNDARY SCAN INTERFACE
Symbol
RD/WR
Symbol Lead No.
DTACK
D(7-0)
RDY /
WR /
RD /
SEL
LDS
INT/
IRQ
TCK
AB5, AA6,
Lead No.
W7, AB4,
AA5, Y6,
Y7, W8
AA3
AA11
AB11
AB13
AA12
Y11
Proprietary TranSwitch Corporation Information for use Solely by its Customers
I/O/P
I/O(T)
I/O/P
O(T)
I
O
I
I
I
CMOS3V
CMOS3V
CMOS3V
TTL3V
Type
TTL3V/
TTL3V
TTL3V
TTL3V
Type
8mA
8mA
8mA
DATA SHEET
IEEE 1149.1 Test Port Serial Scan Clock: This signal is used to
shift data into TDI on the rising edge, and out of TDO on the falling
edge. The maximum clock frequency is 10 MHz.
Data Bus (Motorola/Intel Buses): Bidirectional data lines used for
transferring data to or from a memory map location. D7 (lead AA5) is
the most significant bit.
Select: An active low enables data transfers between the micropro-
cessor and the memory map location during a read/write cycle.
Read (I mode) or Read/Write (M mode):
Intel Mode - An active low signal generated by the microprocessor
for reading memory map locations.
Motorola Mode - An active high signal generated by the micropro-
cessor for reading the memory map locations. An active low signal is
used to write to memory map locations.
Write (I mode) or Device Select (M mode):
Intel Mode - An active low signal generated by the microprocessor
for writing to memory map locations.
Motorola Mode - The SEL and LDS inputs are logically OR-gated
inside the device, generating an internal active low select signal (CS)
that is similar to SEL. This internal signal is used to enable data
transfer. This lead can be used for the interface with the Motorola
68302 microprocessor. If this lead is not used, it should be tied to
ground.
Ready (I mode) or Data Transfer Acknowledge (M mode):
Intel Mode - A high is an acknowledgment from the addressed mem-
ory map location that the transfer can be completed. A low indicates
that the Mapper cannot complete the transfer cycle, and that micro-
processor wait states must be generated.
Motorola Mode - During a read bus cycle, a low signal indicates that
the information on the data bus is valid. During a write bus cycle, a
low signal acknowledges the acceptance of data.
Interrupt: A high on this output lead signals an interrupt request INT
to the microprocessor, as required for Intel compatibility micropro-
cessors. For Motorola operation, a low signals an interrupt request
IRQ to the microprocessor.
Please note: it will take approximately 4 microseconds before the
interrupt is asserted after the last enabling mask bit is set to 1. The
interrupt is asserted immediately when the gating event is the
latched alarm.
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