TXC-04222-AIOG Transwitch Corporation, TXC-04222-AIOG Datasheet - Page 194

• Manufacturer Part Number: TXC-04222-AIOG
• Manufacturer: Transwitch Corporation

Specifications of TXC-04222-AIOG

• Screening Level: Industrial
• Package Type: BGA
• Lead Free Status / Rohs Status: Not Compliant

June 2003
TEMx28
TXC-04222
TXC-04222-MB, Ed. 6
Address
X+0D1
X+0D2
X+0D3
7-0
7-0
Bit
7
6
5
Proprietary TranSwitch Corporation Information for use Solely by its Customers
BTnTCAIS
BTnTPTV
BTnGAIS
Add Bus
Add Bus
Symbol
N2 Byte
K4 Byte
B Side
B Side
B side Add Bus Channel n N2 byte: The value written to this location is
transmitted as the N2 byte for the VT/TU selected for the B side add bus
and when control bit ATnTCEN (bit 2, register X+0D3H) is 0. Bits 7-0 of the
register correspond to bits 1-8 of the N2 byte.
B Side Add Bus Channel n K4 Byte: The value written to this location is
transmitted as the K4 byte for the VT/TU selected for the B side add bus
and when control bit BTnK4PC (bit 1, register 0D5H) is 1. When control bit
BTnK4PC is set to 0, the bits transmitted from this register are a function
of the RDI and line interface options. When the three bit RDI feature is
enabled, the value in bits 5, 6, and 7 are ignored. When the single bit RDI
feature is enabled, bits 5, 6, and 7 from this register are transmitted. When
the VT symmetrical clock interface is enabled, bits 1 and 2 in this register
are ignored. Bits 3, 4, and 8 are always transmitted from this register. Bits
7-0 of the register correspond to bits 1-8 of the K4 byte.
B Side Add Bus Channel n Transmit Tandem Connection AIS:
Enabled when control bit BTnTCEN is a 1. A 1 causes bit 4 in the N2 byte
to be transmitted as a 1.
B Side Add Bus Channel n Transmit VT/TU AIS: A 1 enables a TU/VT
AIS to be transmitted for the TU/VT selected for the B side add bus. A
TU/VT AIS consists of all ones in the entire TU/VT, including the V1
through V4 bytes.
B Side Add Bus Channel n Transmit VT/TU V1/V2 Test Pointer Bytes:
A 1 enables the test pointer value written to registers X+0CCH (V1 byte)
and X+0CDH (V2 byte) by the microprocessor to be transmitted.
Please note that the pointer offset for the overhead bytes (e.g., V5 byte)
and the payload will remain fixed.
DATA SHEET
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Description