TXC-04222-AIOG Transwitch Corporation, TXC-04222-AIOG Datasheet - Page 148

• Manufacturer Part Number: TXC-04222-AIOG
• Manufacturer: Transwitch Corporation

Specifications of TXC-04222-AIOG

• Screening Level: Industrial
• Package Type: BGA
• Lead Free Status / Rohs Status: Not Compliant

June 2003
TEMx28
TXC-04222
TXC-04222-MB, Ed. 6
Address
009
Bit
7
6
5
4
3
2
1
0
Proprietary TranSwitch Corporation Information for use Solely by its Customers
MDJ2LOL
MDJ2TIM
Symbol
MTLOS
MTLOC
MTFFE
MTAIS
MOOL
Not used:
Mask Bit Transmit Line AIS Alarm All Channels: A 1 enables a chan-
nel polling register bit for the A and B add sides to set when a transmit
line AIS latched alarm occurs in any channel. A 0 disables a transmit line
AIS label latched alarm in any channel from setting the corresponding
polling bit.
Mask Bit Transmit FIFO Alarm All Channels: A 1 enables a channel
polling register bit for the A and B add sides to set when a transmit FIFO
latched alarm occurs in any channel. A 0 disables a transmit FIFO
latched alarm in any channel from setting the corresponding polling bit.
Mask Bit PRBS Analyzer Out Of lock Alarm: A 1 enables a channel
polling register bit for the PRBS analyzer to set when an out of lock
latched alarm occurs in any channel. A 0 disables a out of lock latched
alarm in any channel from setting the corresponding polling bit.
Mask Bit Transmit Loss Of Signal Alarm All Channels: A 1 enables a
channel polling register bit for the A and B add sides to set when a trans-
mit loss of signal latched alarm occurs in any channel. A 0 disables a
transmit LOS latched alarm in any channel from setting the correspond-
ing polling bit.
Mask Bit Transmit Loss Of Clock Alarm All Channels: A 1 enables a
channel polling register bit for the A and B add sides to set when a trans-
mit loss of clock latched alarm occurs in any channel. A 0 disables a
transmit LOC latched alarm in any channel from setting the correspond-
ing polling bit.
Mask Bit J2 Trace Mismatch Alarm A and B Drop All Channels: A 1
enables a channel polling register bit for the A and B drop sides to set
when a J2 trace mismatch latched alarm occurs in any channel. A 0 dis-
ables a J2 trace mismatch latched alarm in any channel from setting the
corresponding polling bit.
Mask Bit J2 Loss Of Lock Alarm A and B Drop All Channels: A 1
enables a channel polling register bit for the A and B drop sides to set
when a J2 loss of lock mismatch latched alarm occurs in any channel. A
0 disables a J2 loss of lock latched alarm in any channel from setting the
corresponding polling bit.
DATA SHEET
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