TXC-04222-AIOG Transwitch Corporation, TXC-04222-AIOG Datasheet - Page 182

• Manufacturer Part Number: TXC-04222-AIOG
• Manufacturer: Transwitch Corporation

Specifications of TXC-04222-AIOG

• Screening Level: Industrial
• Package Type: BGA
• Lead Free Status / Rohs Status: Not Compliant

June 2003
TEMx28
TXC-04222
TXC-04222-MB, Ed. 6
Address
X+003
X+004
7-2
7-6
Bit
1
0
5
4
3
2
1
0
Proprietary TranSwitch Corporation Information for use Solely by its Customers
EXnLOSP
EXnLOS
Symbol
TnPRN
TnPTG
TnANZ
LnLBK
FnLBK
Not used:
Transmit External Loss Of Signal Enable: Enabled only when the trans-
mit NRZ interface is selected. A 1 configures the negative rail interface
lead for an external loss of signal indication, A 0 configures the negative
rail interface lead for external coding violations. The coding violation active
true state is positive.
Transmit External Loss Of Signal Sense Selection: Enabled only when
control bit EXnLOS above is a 1. A 1 configures the loss of signal active
true state to be positive. A 0 configures the loss of signal active true state
to be negative.
Not used:
PBRS Generator Enable: A 1 enables the PRBS generator for channel n.
The PRBS pattern is selected by control bit TnPRN.
PRBS Analyzer Enable: A 1 enables the PRBS analyzer for channel n.
The PRBS pattern is selected by control bit TnPRN.
Not used:
PRBS Pattern Selection: The test generator and analyzer PRBS pattern
is selected according to the following table.
TnPRN
0
1
Line Loopback: A 1 enables a DS1 or E1 line side loopback for channel
n. The receive line side DS1 or E1 clock and data output signals are
looped back internally as the DS1 or E1 transmit input signals. The exter-
nal DS1 or E1 transmit clock and data input signals are disabled. The DS1
or E1 receive clock and data output signals or line AIS are provided at the
receive interface, depending on the sate of control bit RnLAIS (bit 0,
X+000H). This control bit works in conjunction with control bit FnLBK (see
bit 0 below) to provide a bidirectional loopback. When this control bit and
FnLBK are both set to 1, bidirectional loopback is enabled. In this mode of
operation, the transmit data is looped back as receive data, and the output
of the demapper is looped back as transmit data. The RnCLKI (bit 3, regis-
ter X+000H) and TnCLKI (bit 3, register X+002H) control bits must be pro-
grammed for opposite edges when using Line Loopback or Bidirectional
Loopback.
Facility Loopback: A 1 enables a DS1 or E1 facility (side) loopback for
channel n. The DS1 or E1 transmit clock and data output signals are
looped back internally as the DS1 or E1 receive clock and data input sig-
nals. The external DS1 or E1 receive input signals are disabled. The DS1
or E1 transmit clock and data output signals are provided at the interface.
DATA SHEET
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PRBS Pattern
2
2
15
20
-1 pattern.
-1 QRS pattern.
Description