TXC-04222-AIOG Transwitch Corporation, TXC-04222-AIOG Datasheet - Page 85

• Manufacturer Part Number: TXC-04222-AIOG
• Manufacturer: Transwitch Corporation

Specifications of TXC-04222-AIOG

• Screening Level: Industrial
• Package Type: BGA
• Lead Free Status / Rohs Status: Not Compliant

Add Bus Parity Selection
The parity selection for two add buses, A and B Add, is according to the following table:
ADD Indicator Invert
An option is provided that inverts the add indicator (AADD and BADD) leads. When a 1 is written to control bit
ADDIV (bit 0, 03AH), the output sense of the two leads is active high when a time slot for channel n is being
added to a bus. When set to 0, the output sense of the two leads is active low when a time slot for channel n is
being added to a bus.
Force Bus to a High Impedance State
An option is provided that can force either of the output add bus signals to a high impedance state, indepen-
dent of the channel selections. When control bit BAHZE (bit 2, 03AH) for the B side or AAHZE (bit 1, 03AH) for
the A side is written with a 1, the following add bus signals are forced to a high impedance state: data
(A/BD(7-0), parity, (A/BPAR), and Add indicator (A/BADD). If enabled as output signals, the following leads are
also forced to a high impedance state: clock (A/BCLK), C1, J1, and V1 marker pulses (A/BC1J1V1), and the
payload indication (A/BSPE).
Force Channel N to a High Impedance State
The data and add indication corresponding to a channel can be forced to a high impedance state in two way.
The A and B Add Bus VT/TU selection register is written to 00H, or control bit AnHIGHZ (bit 0, X+065H) or
BnHIGHZ (bit 0, 0D5H) is written with a 1.
ADD Bus Delay
Normally there is one clock cycle of delay between the add bus data (A/BD(7-0)) and the timing signals such
as A/BSPE (add bus timing), or timing signals from the corresponding drop bus in the drop bus timing mode.
The delay may be increased to two clock cycles when control bit ABOD (bit 1, 03BH) is written with a 1.
(bit 5, 03AH)
Proprietary TranSwitch Corporation Information for use Solely by its Customers
ABPE
0
0
1
1
(bit 6, 03AH)
PADO
0
1
0
1
Odd parity is calculated for the output leads consisting
of data (A/BA(7-0)) in the drop bus timing mode, and
also the output leads: clock (A/BACLK), C1, J1, and
V1 marker pulses (A/BAC1J1V1), and payload indica-
tion (A/BASPE) when they are provided as outputs in
the drop bus timing mode.
Odd parity is calculated for the data output leads
(A/BA(7-0)).
Even parity is calculated for the output leads consisting
of data (A/BA(7-0)) in the drop bus timing mode, and
also the output leads: clock (A/BACLK), C1, J1, and
V1 marker pulses (A/BAC1J1V1), and payload indica-
tion (A/BASPE) when they are provided as outputs in
the drop bus timing mode.
Even parity is calculated for the data output leads
(A/BA(7-0)).
DATA SHEET
- 85 of 246 -
Add Bus Parity Selection
TXC-04222-MB, Ed. 6
TXC-04222
TEMx28
June 2003