ST7LITE49K2 STMicroelectronics, ST7LITE49K2 Datasheet - Page 105

• Manufacturer Part Number: ST7LITE49K2
• Description: 8-bit MCU
• Manufacturer: STMicroelectronics

Specifications of ST7LITE49K2

• 8 Kbytes Single Voltage Extended Flash (xflash) Program Memory With Read-out Protection In-circuit Programming And In-application Programming (icp And Iap) Endurance: 10K write/erase cycles guaranteed Data retention
• 256 Bytes Data Eeprom With Read-out Protection. 300k Write/erase Cycles Guaranteed, Data Retention: 20 years at 55 °C.
• Clock Sources: Internal trimmable 8 MHz RC oscillator, auto-wakeup internal low power - low frequency oscillator, crystal/ceramic resonator or external clock
• Five Power Saving Modes: Halt, Active-halt, Auto-wakeup from Halt, Wait and Slow

ST7LITE49K2
Note:
Note:
Note:
Timer control register 2 (ATCSR2)
Reset value: 0000 0011 (03h)
Bit 7 = FORCE2 Force counter 2 overflow bit
This bit must not be reset by software
Bit 6 = FORCE1 Force counter 1 overflow bit
This bit must not be reset by software
Bit 5 = ICS Input capture shorted bit
Bit 4 = OVFIE2 Overflow interrupt 2 enable bit
Bit 3 = OVF2 Overflow flag
Bit 2 = ENCNTR2 Enable counter2 for PWM2/3
Counter 2 gets frozen when the ENCNTR2 bit is reset. When ENCNTR2 is set again, the
counter will restart from the last value.
FORCE2
This bit is read/set by software. When set, it loads FFFh in the CNTR2 register. It is
reset by hardware one CPU clock cycle after counter 2 overflow has occurred.
0 : No effect on CNTR2
1 : Loads FFFh in CNTR2
This bit is read/set by software. When set, it loads FFFh in CNTR1 register. It is reset
by hardware one CPU clock cycle after counter 1 overflow has occurred.
0 : No effect on CNTR1
1 : Loads FFFh in CNTR1
This bit is read/write by software. It allows the ATtimer CNTR1 to use the LTIC pin for
long Input Capture.
0 : ATIC for CNTR1 Input Capture
1 : LTIC for CNTR1 Input Capture
This bit is read/write by software and controls the overflow interrupt of counter2.
0: Overflow interrupt disabled.
1: Overflow interrupt enabled.
This bit is set by hardware and cleared by software by reading the ATCSR2 register. It
indicates the transition of the counter2 from FFFh to ATR2 value.
0: No counter overflow occurred
1: Counter overflow occurred
This bit is read/write by software and switches the PWM2/3 operation to the CNTR2
counter. If this bit is set, PWM2/3 will be generated using CNTR2.
0: PWM2/3 is generated using CNTR1.
1: PWM2/3 is generated using CNTR2.
7
FORCE1
ICS
OVFIE2
Read/write
OVF2
ENCNTR2
On-chip peripherals
TRAN2
TRAN1
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