ST7LITE49K2 STMicroelectronics, ST7LITE49K2 Datasheet - Page 133

• Manufacturer Part Number: ST7LITE49K2
• Description: 8-bit MCU
• Manufacturer: STMicroelectronics

Specifications of ST7LITE49K2

• 8 Kbytes Single Voltage Extended Flash (xflash) Program Memory With Read-out Protection In-circuit Programming And In-application Programming (icp And Iap) Endurance: 10K write/erase cycles guaranteed Data retention
• 256 Bytes Data Eeprom With Read-out Protection. 300k Write/erase Cycles Guaranteed, Data Retention: 20 years at 55 °C.
• Clock Sources: Internal trimmable 8 MHz RC oscillator, auto-wakeup internal low power - low frequency oscillator, crystal/ceramic resonator or external clock
• Five Power Saving Modes: Halt, Active-halt, Auto-wakeup from Halt, Wait and Slow

ST7LITE49K2
Note:
Note:
If the external clock pin is not available, programming the external clock configuration stops
the counter.
Bit 1 = IEDG2 Input edge 2
Bit 0 = EXEDG External clock edge
Timer A control/status register (TACSR)
Reset value: 0000 0000 (00h)
The 3 least significant bits are not used.
Bit 7 = ICF1 Input capture flag 1
Bit 6 = OCF1 Output compare flag 1
Bit 5 = TOF Timer overflow flag
Reading or writing the ACLR register does not clear TOF.
ICF1
10: Timer clock = f
11: Timer clock = external clock (where available)
This bit determines which type of level transition on the ICAP2 pin triggers the capture.
0: A falling edge triggers the capture
1: A rising edge triggers the capture
This bit determines which type of level transition on the external clock pin EXTCLK
triggers the counter register.
0: A falling edge triggers the counter register
1: A rising edge triggers the counter register
0: No input capture (reset value)
1: An input capture has occurred on the ICAP1 pin or the counter has reached the
OC2R value in PWM mode. To clear this bit, first read the SR register, then read or
write the low byte of the IC1R (IC1LR) register.
0: No match (reset value)
1: The content of the free running counter has matched the content of the OC1R
register. To clear this bit, first read the SR register, then read or write the low byte of
the OC1R (OC1LR) register.
0: No timer overflow (reset value)
1: The free running counter rolled over from FFFFh to 0000h. To clear this bit, first
read the SR register, then read or write the low byte of the CR (CLR) register.
7
OCF1
CPU
TOF
/8
ICF2
Read Only
OCF2
TIMD
On-chip peripherals
Reserved
133/245
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