ST7LITE49K2 STMicroelectronics, ST7LITE49K2 Datasheet - Page 123

• Manufacturer Part Number: ST7LITE49K2
• Description: 8-bit MCU
• Manufacturer: STMicroelectronics

Specifications of ST7LITE49K2

• 8 Kbytes Single Voltage Extended Flash (xflash) Program Memory With Read-out Protection In-circuit Programming And In-application Programming (icp And Iap) Endurance: 10K write/erase cycles guaranteed Data retention
• 256 Bytes Data Eeprom With Read-out Protection. 300k Write/erase Cycles Guaranteed, Data Retention: 20 years at 55 °C.
• Clock Sources: Internal trimmable 8 MHz RC oscillator, auto-wakeup internal low power - low frequency oscillator, crystal/ceramic resonator or external clock
• Five Power Saving Modes: Halt, Active-halt, Auto-wakeup from Halt, Wait and Slow

ST7LITE49K2
Note:
1
2
3
4
5
The OC
the following formula:
Equation 1
Where:
Δ
f
PRESC
If the timer clock is an external clock, the formula is:
Equation 2
Where:
Δ
f
Clearing the output compare interrupt request (that is, clearing the OCFi bit) is done by:
1.
2.
The following procedure is recommended to prevent the OCFi bit from being set between
the time it is read and the time it is written to the OC
●
●
●
After a processor write cycle to the OCiHR register, the output compare function is inhibited
until the OCiLR register is also written.
If the OCiE bit is not set, the OCMPi pin is a general I/O port and the OLVLi bit does not
appear when a match is found but an interrupt could be generated if the OCIE bit is set.
In both internal and external clock modes, OCFi and OCMPi are set while the counter value
equals the OCiR register value (see
an example with f
The output compare functions can be used both for generating external events on the
OCMPi pins even if the input capture mode is also used.
The value in the 16-bit OC
successful comparison in order to control an output waveform or establish a new elapsed
timeout.
CPU
EXT
t =
t =
=
Reading the SR register while the OCFi bit is set.
Accessing (reading or writing) the OCiLR register.
Write to the OCiHR register (further compares are inhibited).
Read the SR register (first step in the clearance of the OCFi bit, which may be already
set).
Write to the OCiLR register (enables the output compare function and clears the OCFi
bit).
=
=
i
R register value required for a specific timing application can be calculated using
Δ
output compare period (in seconds)
CPU clock frequency (in hertz)
timer prescaler factor (2, 4 or 8 depending on CC[1:0] bits, see
register 2 (TACR2) on page
output compare period (in seconds)
external timer clock frequency (in hertz)
OCiR =
CPU
Δt
/4). This behavior is the same in OPM or PWM mode.
*
f
EXT
i
R register and the OLVi bit should be changed after each
Δ
Figure 63
OCiR =
132)
for an example with f
Δt
PRESC
*
f
CPU
i
R register:
CPU
On-chip peripherals
/2 and
: Timer A control
Figure 64
123/245
for