ST7LITE49K2 STMicroelectronics, ST7LITE49K2 Datasheet - Page 116
ST7LITE49K2
Manufacturer Part Number
ST7LITE49K2
Description
8-bit MCU
Manufacturer
STMicroelectronics
Datasheet
1.ST7LITE49K2.pdf
(245 pages)
Specifications of ST7LITE49K2
8 Kbytes Single Voltage Extended Flash (xflash) Program Memory With Read-out Protection In-circuit Programming And In-application Programming (icp And Iap) Endurance
10K write/erase cycles guaranteed Data retention
256 Bytes Data Eeprom With Read-out Protection. 300k Write/erase Cycles Guaranteed, Data Retention
20 years at 55 °C.
Clock Sources
Internal trimmable 8 MHz RC oscillator, auto-wakeup internal low power - low frequency oscillator, crystal/ceramic resonator or external clock
Five Power Saving Modes
Halt, Active-halt, Auto-wakeup from Halt, Wait and Slow
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On-chip peripherals
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Counter register (CR)
●
●
Alternate counter register (ACR)
●
●
These two read-only 16-bit registers contain the same value but with the difference that
reading the ACLR register does not clear the TOF bit (timer overflow flag), located in the
status register, (SR),
alternate counter register) on page
Writing in the CLR register or ACLR register resets the free running counter to the FFFCh
value. Both counters have a reset value of FFFCh (this is the only value which is reloaded in
the 16-bit timer). The reset value of both counters is also FFFCh in One Pulse mode and
PWM mode.
The timer clock depends on the clock control bits of the CR2 register, as illustrated in
Table
clock cycles depending on the CC[1:0] bits. The timer frequency can be f
f
CPU
/8 or an external frequency.
Counter high register (CHR) is the most significant byte (MSB).
Counter low register (CLR) is the least significant byte (LSB).
Alternate counter high register (ACHR) is the MSB.
Alternate counter low register (ACLR) is the LSB.
37. The value in the counter register repeats every 131 072, 262 144 or 524 288 CPU
(see16-bit read sequence (from either the counter register or the
118).
CPU
/2, f
ST7LITE49K2
CPU
/4,
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