ST7LITE49K2 STMicroelectronics, ST7LITE49K2 Datasheet - Page 21

• Manufacturer Part Number: ST7LITE49K2
• Description: 8-bit MCU
• Manufacturer: STMicroelectronics

Specifications of ST7LITE49K2

• 8 Kbytes Single Voltage Extended Flash (xflash) Program Memory With Read-out Protection In-circuit Programming And In-application Programming (icp And Iap) Endurance: 10K write/erase cycles guaranteed Data retention
• 256 Bytes Data Eeprom With Read-out Protection. 300k Write/erase Cycles Guaranteed, Data Retention: 20 years at 55 °C.
• Clock Sources: Internal trimmable 8 MHz RC oscillator, auto-wakeup internal low power - low frequency oscillator, crystal/ceramic resonator or external clock
• Five Power Saving Modes: Halt, Active-halt, Auto-wakeup from Halt, Wait and Slow

ST7LITE49K2
3
Caution:
Table 3.
Address
0009h to
000Bh
000Ch
000Dh
000Eh
000Fh
0000h
0001h
0002h
0003h
0004h
0005h
0006h
0007h
0008h
0010h
Register and memory mapping
As shown in
registers.
The available memory locations consist of 128 bytes of register locations, 384 bytes of
RAM, 256 bytes of data EEPROM and 8 Kbytes of Flash program memory. The RAM space
includes up to 128 bytes for the stack from 180h to 1FFh.
The highest address bytes contain the user reset and interrupt vectors.
The Flash memory contains two sectors (see ) mapped in the upper part of the ST7
addressing space so the reset and interrupt vectors are located in Sector 0 (FFE0h-FFFFh).
The size of Flash Sector 0 and other device options are configurable by option bytes (refer
to
Memory locations marked as “Reserved” must never be accessed. Accessing a reserved
area can have unpredictable effects on the device.
Hardware register map
TIMER
Port A
Port B
Port C
Block
LITE
Section 14.1 on page
Register label
Figure
LTCNTR
LTCSR2
LTCSR1
PBDDR
PCDDR
PADDR
LTARR
PBDR
PBOR
PCDR
PCOR
LTICR
PADR
PAOR
4, the MCU is capable of addressing 64 Kbytes of memories and I/O
(1)
230).
Lite Timer Control/Status register 2
Lite Timer Control/Status register 1
Lite Timer Input Capture register
Lite Timer Auto-reload register
Port C Data Direction register
Port A Data Direction register
Port B Data Direction register
Lite Timer Counter register
Reserved area (3 bytes)
Port C Option register
Port A Option register
Port B Option register
Port C Data register
Port A Data register
Port B Data register
Register name
Register and memory mapping
Reset status
0x00 0000b
0Fh
00h
00h
00h
00h
00h
00h
00h
00h
08h
00h
00h
xxh
Read Only
Read Only
Remarks
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
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