ST7LITE49K2 STMicroelectronics, ST7LITE49K2 Datasheet - Page 140

• Manufacturer Part Number: ST7LITE49K2
• Description: 8-bit MCU
• Manufacturer: STMicroelectronics

Specifications of ST7LITE49K2

• 8 Kbytes Single Voltage Extended Flash (xflash) Program Memory With Read-out Protection In-circuit Programming And In-application Programming (icp And Iap) Endurance: 10K write/erase cycles guaranteed Data retention
• 256 Bytes Data Eeprom With Read-out Protection. 300k Write/erase Cycles Guaranteed, Data Retention: 20 years at 55 °C.
• Clock Sources: Internal trimmable 8 MHz RC oscillator, auto-wakeup internal low power - low frequency oscillator, crystal/ceramic resonator or external clock
• Five Power Saving Modes: Halt, Active-halt, Auto-wakeup from Halt, Wait and Slow

On-chip peripherals
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Mode selection
The interface can operate in the four following modes:
●
●
By default, it operates in slave mode.
The interface automatically switches from slave to master after it generates a START
condition and from master to slave in case of arbitration loss or a STOP generation, allowing
then Multi-Master capability.
Communication flow
In Master mode, it initiates a data transfer and generates the clock signal. A serial data
transfer always begins with a start condition and ends with a stop condition. Both start and
stop conditions are generated in master mode by software.
In Slave mode, the interface is capable of recognizing its own address (7 or 10-bit), and the
General Call address. The General Call address detection may be enabled or disabled by
software.
Data and addresses are transferred as 8-bit bytes, MSB first. The first byte(s) following the
start condition contain the address (one in 7-bit mode, two in 10-bit mode). The address is
always transmitted in Master mode.
A 9th clock pulse follows the 8 clock cycles of a byte transfer, during which the receiver must
send an acknowledge bit to the transmitter. Refer to
Figure 69. I
Acknowledge may be enabled and disabled by software.
The I
The speed of the I
I
SDA/SCL line control
Transmitter mode: the interface holds the clock line low before transmission to wait for the
microcontroller to write the byte in the Data register.
Receiver mode: the interface holds the clock line low after reception to wait for the
microcontroller to read the byte in the Data register.
The SCL frequency (F
the I
2
C (up to 400 kHz).
2
Slave transmitter/receiver
Master transmitter/receiver
2
C bus mode.
C interface address and/or general call address can be selected by software.
SCL
SDA
CONDITION
2
C bus protocol
START
2
C interface may be selected between Standard (up to 100 kHz) and Fast
scl
) is controlled by a programmable clock divider which depends on
MSB
1
2
8
Figure
ACK
9
69.
CONDITION
STOP
ST7LITE49K2