ST7LITE49K2 STMicroelectronics, ST7LITE49K2 Datasheet - Page 159

• Manufacturer Part Number: ST7LITE49K2
• Description: 8-bit MCU
• Manufacturer: STMicroelectronics

Specifications of ST7LITE49K2

• 8 Kbytes Single Voltage Extended Flash (xflash) Program Memory With Read-out Protection In-circuit Programming And In-application Programming (icp And Iap) Endurance: 10K write/erase cycles guaranteed Data retention
• 256 Bytes Data Eeprom With Read-out Protection. 300k Write/erase Cycles Guaranteed, Data Retention: 20 years at 55 °C.
• Clock Sources: Internal trimmable 8 MHz RC oscillator, auto-wakeup internal low power - low frequency oscillator, crystal/ceramic resonator or external clock
• Five Power Saving Modes: Halt, Active-halt, Auto-wakeup from Halt, Wait and Slow

ST7LITE49K2
Note:
Note:
Note:
Caution:
Figure 75. Generic SS timing diagram
Figure 76. Hardware/software slave select management
Master mode operation
In master mode, the serial clock is output on the SCK pin. The clock frequency, polarity and
phase are configured by software (refer to the description of the SPICSR register).
The idle state of SCK must correspond to the polarity selected in the SPICSR register (by
pulling up SCK if CPOL = 1 or pulling down SCK if CPOL = 0).
How to operate the SPI in master mode
To operate the SPI in master mode, perform the following steps in order:
1.
The slave must have the same CPOL and CPHA settings as the master.
2.
3.
MSTR and SPE bits remain set only if SS is high).
if the SPICSR register is not written first, the SPICR register setting (MSTR bit) may be not
taken into account.
The transmit sequence begins when software writes a byte in the SPIDR register.
Write to the SPICR register:
–
–
Write to the SPICSR register:
–
Write to the SPICR register:
–
MOSI/MISO
Master SS
Slave SS
(if CPHA = 0)
Slave SS
(if CPHA = 1)
Select the clock frequency by configuring the SPR[2:0] bits.
Select the clock polarity and clock phase by configuring the CPOL and CPHA bits.
Figure 77
Either set the SSM bit and set the SSI bit or clear the SSM bit and tie the SS pin
high for the complete byte transmit sequence.
Set the MSTR and SPE bits
shows the four possible configurations.
SS
external pin
SSI bit
Byte 1
SSM bit
1
0
Byte 2
SS
internal
Byte 3
On-chip peripherals
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