ST7LITE49K2 STMicroelectronics, ST7LITE49K2 Datasheet - Page 121

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ST7LITE49K2

Manufacturer Part Number
ST7LITE49K2
Description
8-bit MCU
Manufacturer
STMicroelectronics
Datasheet

Specifications of ST7LITE49K2

8 Kbytes Single Voltage Extended Flash (xflash) Program Memory With Read-out Protection In-circuit Programming And In-application Programming (icp And Iap) Endurance
10K write/erase cycles guaranteed Data retention
256 Bytes Data Eeprom With Read-out Protection. 300k Write/erase Cycles Guaranteed, Data Retention
20 years at 55 °C.
Clock Sources
Internal trimmable 8 MHz RC oscillator, auto-wakeup internal low power - low frequency oscillator, crystal/ceramic resonator or external clock
Five Power Saving Modes
Halt, Active-halt, Auto-wakeup from Halt, Wait and Slow

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ST7LITE49K2
Figure 60. Input capture block diagram
Figure 61. Input capture timing diagram
1. The active edge is the rising edge.
2. The time between an event on the ICAPi pin and the appearance of the corresponding flag is from 2 to 3 CPU clock cycles.
ICAP2
ICAP1
pin
This depends on the moment when the ICAP event happens relative to the timer clock.
pin
6
Counter register
ICAPi register
the user toggle the output pin and if the ICIE bit is set. This can be avoided if the input
capture function i is disabled by reading the ICiHR (see note 1).
The TOF bit can be used with interrupt in order to measure event that go beyond the timer
range (FFFFh).
Timer clock
16-bit
ICAPi flag
ICAPi pin
IC2R register
Edge detect
16-bit free running counter
circuit 2
FF01
Edge detect
IC1R register
circuit 1
FF02
ICF1
ICIE
FF03
ICF2
CC1
FF03
On-chip peripherals
CR1 (control register 1)
CR2 (control register 2)
CC0
SR (status register)
0
IEDG2
IEDG1
0
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