ST7LITE49K2 STMicroelectronics, ST7LITE49K2 Datasheet - Page 129

• Manufacturer Part Number: ST7LITE49K2
• Description: 8-bit MCU
• Manufacturer: STMicroelectronics

Specifications of ST7LITE49K2

• 8 Kbytes Single Voltage Extended Flash (xflash) Program Memory With Read-out Protection In-circuit Programming And In-application Programming (icp And Iap) Endurance: 10K write/erase cycles guaranteed Data retention
• 256 Bytes Data Eeprom With Read-out Protection. 300k Write/erase Cycles Guaranteed, Data Retention: 20 years at 55 °C.
• Clock Sources: Internal trimmable 8 MHz RC oscillator, auto-wakeup internal low power - low frequency oscillator, crystal/ceramic resonator or external clock
• Five Power Saving Modes: Halt, Active-halt, Auto-wakeup from Halt, Wait and Slow

ST7LITE49K2
Note:
11.4.4
1
2
3
4
The OC
the following formula:
Equation 5
Where:
t =
f
PRESC
If the timer clock is an external clock the formula is:
Equation 6
Where:
t =
f
The output compare 2 event causes the counter to be initialized to FFFCh (see
The OCF1 and OCF2 bits cannot be set by hardware in PWM mode therefore the output
compare interrupt is inhibited.
The ICF1 bit is set by hardware when the counter reaches the OC2R value and can produce
a timer interrupt if the ICIE bit is set and the I bit is cleared.
In PWM mode the ICAP1 pin can not be used to perform input capture because it is
disconnected to the timer. The ICAP2 pin can be used to perform input capture (ICF2 can be
set and IC2R can be loaded) but the user must take care that the counter is reset each
period and ICF1 can also generates interrupt if ICIE is set.
When the pulse width modulation (PWM) and one pulse mode (OPM) bits are both set, the
PWM mode is the only active one.
Low power modes
Table 42.
CPU
EXT
Mode
Wait
Halt
=
=
=
i
R register value required for a specific timing application can be calculated using
No effect on 16-bit timer.
Timer interrupts cause the device to exit from Wait mode.
16-bit timer registers are frozen.
In Halt mode, the counter stops counting until Halt mode is exited. Counting resumes from
the previous count when the device is woken up by an interrupt with ‘exit from Halt mode’
capability or from the counter reset value when the device is woken up by a reset.
If an input capture event occurs on the ICAPi pin, the input capture detection circuitry is
armed. Consequently, when the device is woken up by an interrupt with ‘exit from Halt
mode’ capability, the ICFi bit is set, and the counter value present when exiting from Halt
mode is captured into the ICiR register.
OCiR =
signal or pulse period (in seconds)
external timer clock frequency (in hertz)
signal or pulse period (in seconds)
CPU clock frequency (in hertz)
timer prescaler factor (2, 4 or 8 depending on CC[1:0] bits, see
register 2 (TACR2) on page
Effect of low power modes on 16-bit timer
t
*
f
EXT
-5
OCiR value =
132)
Description
PRESC
t
*
f
CPU
- 5
On-chip peripherals
: Timer A control
Figure
129/245
67)