ST7LITE49K2 STMicroelectronics, ST7LITE49K2 Datasheet - Page 125

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ST7LITE49K2

Manufacturer Part Number
ST7LITE49K2
Description
8-bit MCU
Manufacturer
STMicroelectronics
Datasheet

Specifications of ST7LITE49K2

8 Kbytes Single Voltage Extended Flash (xflash) Program Memory With Read-out Protection In-circuit Programming And In-application Programming (icp And Iap) Endurance
10K write/erase cycles guaranteed Data retention
256 Bytes Data Eeprom With Read-out Protection. 300k Write/erase Cycles Guaranteed, Data Retention
20 years at 55 °C.
Clock Sources
Internal trimmable 8 MHz RC oscillator, auto-wakeup internal low power - low frequency oscillator, crystal/ceramic resonator or external clock
Five Power Saving Modes
Halt, Active-halt, Auto-wakeup from Halt, Wait and Slow

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ST7LITE49K2
Figure 64. Output compare timing diagram, f
One pulse mode
One pulse mode enables the generation of a pulse when an external event occurs. This
mode is selected via the OPM bit in the CR2 register.
The one pulse mode uses the input capture1 function and the output compare1 function.
Procedure
1.
2.
3.
Load the OC1R register with the value corresponding to the length of the pulse (see
Equation 3
Select the following in the CR1 register:
Select the following in the CR2 register:
Using the OLVL1 bit, select the level to be applied to the OCMP1 pin after the
pulse.
Using the OLVL2 bit, select the level to be applied to the OCMP1 pin during the
pulse.
Select the edge of the active transition on the ICAP1 pin with the IEDG1 bit (the
ICAP1 pin must be configured as floating input).
Set the OC1E bit, the OCMP1 pin is then dedicated to the output compare 1
function.
Set the OPM bit.
Select the timer clock CC[1:0] (see
page
Output compare register i (OCRi)
Output compare flag i (OCFi)
132).
below).
OCMPi pin (OLVLi = 1)
Internal CPU clock
Counter register
Timer clock
2ECF
: Timer A control register 2 (TACR2) on
2ED0
TIMER
2ED1
= f
2ED3
CPU
2ED2
/4
2ED3
On-chip peripherals
2ED4
125/245

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