ST7LITE49K2 STMicroelectronics, ST7LITE49K2 Datasheet - Page 156

• Manufacturer Part Number: ST7LITE49K2
• Description: 8-bit MCU
• Manufacturer: STMicroelectronics

Specifications of ST7LITE49K2

• 8 Kbytes Single Voltage Extended Flash (xflash) Program Memory With Read-out Protection In-circuit Programming And In-application Programming (icp And Iap) Endurance: 10K write/erase cycles guaranteed Data retention
• 256 Bytes Data Eeprom With Read-out Protection. 300k Write/erase Cycles Guaranteed, Data Retention: 20 years at 55 °C.
• Clock Sources: Internal trimmable 8 MHz RC oscillator, auto-wakeup internal low power - low frequency oscillator, crystal/ceramic resonator or external clock
• Five Power Saving Modes: Halt, Active-halt, Auto-wakeup from Halt, Wait and Slow

On-chip peripherals
11.6
11.6.1
11.6.2
Note:
11.6.3
156/245
Serial peripheral interface (SPI)
Introduction
The Serial Peripheral Interface (SPI) allows full-duplex, synchronous, serial communication
with external devices. An SPI system may consist of a master and one or more slaves or a
system in which devices may be either masters or slaves.
Main features
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In slave mode, continuous transmission is not possible at maximum frequency due to the
software overhead for clearing status flags and to initiate the next transmission sequence.
General description
Figure 73 on page 157
three registers:
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The SPI is connected to external devices through four pins:
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Full duplex synchronous transfers (on three lines)
Simplex synchronous transfers (on two lines)
Master or slave operation
6 master mode frequencies (f
f
SS Management by software or hardware
Programmable clock polarity and phase
End of transfer interrupt flag
Write collision, Master mode fault and overrun flags
SPI control register (SPICR)
SPI control/status register (SPICSR)
SPI data register (SPIDR)
MISO: Master in / slave out data
MOSI: Master out / slave In data
SCK: Serial clock out by SPI masters and input by SPI slaves
SS: Slave select: This input signal acts as a ‘chip select’ to let the SPI master
communicate with slaves individually and to avoid contention on the data lines. Slave
SS inputs can be driven by standard I/O ports on the master Device.
CPU
/2 max. slave mode frequency (see note)
shows the serial peripheral interface (SPI) block diagram. There are
CPU
/4 max.)
ST7LITE49K2