ST7LITE49K2 STMicroelectronics, ST7LITE49K2 Datasheet - Page 158

• Manufacturer Part Number: ST7LITE49K2
• Description: 8-bit MCU
• Manufacturer: STMicroelectronics

Specifications of ST7LITE49K2

• 8 Kbytes Single Voltage Extended Flash (xflash) Program Memory With Read-out Protection In-circuit Programming And In-application Programming (icp And Iap) Endurance: 10K write/erase cycles guaranteed Data retention
• 256 Bytes Data Eeprom With Read-out Protection. 300k Write/erase Cycles Guaranteed, Data Retention: 20 years at 55 °C.
• Clock Sources: Internal trimmable 8 MHz RC oscillator, auto-wakeup internal low power - low frequency oscillator, crystal/ceramic resonator or external clock
• Five Power Saving Modes: Halt, Active-halt, Auto-wakeup from Halt, Wait and Slow

On-chip peripherals
158/245
Figure 74. Single master/ single slave application
Slave select management
As an alternative to using the SS pin to control the Slave Select signal, the application can
choose to manage the Slave Select signal by software. This is configured by the SSM bit in
the SPICSR register (see
In software management, the external SS pin is free for other application uses and the
internal SS signal level is driven by writing to the SSI bit in the SPICSR register.
In Master mode:
●
In Slave mode:
There are two cases depending on the data/clock timing relationship (see
If CPHA = 1 (data latched on second clock edge):
●
If CPHA = 0 (data latched on first clock edge):
●
SS internal must be held high continuously
SS internal must be held low during the entire transmission. This implies that in single
slave applications the SS pin either can be tied to V
managing the SS function by software (SSM = 1 and SSI = 0 in the SPICSR register)
SS internal must be held low during byte transmission and pulled high between each
byte to allow the slave to write to the shift register. If SS is not pulled high, a Write
Collision error will occur when the slave writes to the shift register (see
collision error
MSBit
8-BIT SHIFT REGISTER
GENERATOR
CLOCK
SPI
MASTER
(WCOL)).
LSBit
Figure
76).
MOSI
SCK
SS
MISO
+5V
MISO
MOSI
SCK
SS
SS
, or made free for standard I/O by
8-BIT SHIFT REGISTER
MSBit
Not used if SS is managed
by software
SLAVE
Figure
Section : Write
ST7LITE49K2
75):
LSBit