ST7LITE49K2 STMicroelectronics, ST7LITE49K2 Datasheet - Page 47

• Manufacturer Part Number: ST7LITE49K2
• Description: 8-bit MCU
• Manufacturer: STMicroelectronics

Specifications of ST7LITE49K2

• 8 Kbytes Single Voltage Extended Flash (xflash) Program Memory With Read-out Protection In-circuit Programming And In-application Programming (icp And Iap) Endurance: 10K write/erase cycles guaranteed Data retention
• 256 Bytes Data Eeprom With Read-out Protection. 300k Write/erase Cycles Guaranteed, Data Retention: 20 years at 55 °C.
• Clock Sources: Internal trimmable 8 MHz RC oscillator, auto-wakeup internal low power - low frequency oscillator, crystal/ceramic resonator or external clock
• Five Power Saving Modes: Halt, Active-halt, Auto-wakeup from Halt, Wait and Slow

ST7LITE49K2
7.4
Note:
7.4.1
Note:
Caution:
System integrity management (SI)
The System Integrity Management block contains the Low voltage Detector (LVD) and
Auxiliary Voltage Detector (AVD) functions. It is managed by the SICSR register.
Refer to
Low voltage detector (LVD)
The Low Voltage Detector function (LVD) generates a static reset when the V
voltage is below a V
as the power-down keeping the ST7 in reset.
The V
for power-on in order to avoid a parasitic reset when the MCU starts running and sinks
current on the supply (hysteresis).
The LVD Reset circuitry generates a reset when V
●
●
The LVD function is illustrated in
The voltage threshold can be configured by option byte to be low, medium or high. See
Section 14.1 on page
Provided the minimum V
the MCU can only be in two modes:
●
●
In these conditions, secure operation is always ensured for the application without the need
for external reset hardware.
During a Low Voltage Detector Reset, the RESET pin is held low, thus permitting the MCU
to reset other devices.
Use of LVD with capacitive power supply: with this type of power supply, if power cuts occur
in the application, it is recommended to pull V
conditions. Refer to circuit example in
The LVD is an optional function which can be selected by option byte. See
page
It allows the device to be used without any external RESET circuitry.
If the LVD is disabled, an external circuitry must be used to ensure a proper power-on reset.
It is recommended to make sure that the V
device is exiting from Reset, to ensure the application functions properly.
Make sure that the right combination of LVD and AVD thresholds is used as LVD and AVD
levels are not correlated. Refer to section
page 196
If an LVD reset occurs after a watchdog reset has occurred, the LVD will take priority and will
clear the watchdog flag.
A reset can also be triggered following the detection of an illegal opcode or prebyte code.
V
V
Under full software control
In static safe reset
230.
IT-(LVD)
IT+(LVD)
IT-(LVD)
Section 12.2.1 on page 189
for more details.
reference value for a voltage drop is lower than the V
when V
when V
IT-(LVD)
DD
DD
230.
is falling
DD
is rising
reference value. This means that it secures the power-up as well
value (guaranteed for the oscillator frequency) is above V
Figure
for further details.
Figure 122 on page 225
17.
Section 13.3.2 on page 195
DD
DD
supply voltage rises monotonously when the
down to 0 V to ensure optimum restart
DD
Supply, reset and clock management
is below:
and note 4.
IT+(LVD)
and
Section 13.3.3 on
reference value
Section 14.1 on
DD
supply
IT-(LVD)
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