ST7LITE49K2 STMicroelectronics, ST7LITE49K2 Datasheet - Page 181

• Manufacturer Part Number: ST7LITE49K2
• Description: 8-bit MCU
• Manufacturer: STMicroelectronics

Specifications of ST7LITE49K2

• 8 Kbytes Single Voltage Extended Flash (xflash) Program Memory With Read-out Protection In-circuit Programming And In-application Programming (icp And Iap) Endurance: 10K write/erase cycles guaranteed Data retention
• 256 Bytes Data Eeprom With Read-out Protection. 300k Write/erase Cycles Guaranteed, Data Retention: 20 years at 55 °C.
• Clock Sources: Internal trimmable 8 MHz RC oscillator, auto-wakeup internal low power - low frequency oscillator, crystal/ceramic resonator or external clock
• Five Power Saving Modes: Halt, Active-halt, Auto-wakeup from Halt, Wait and Slow

ST7LITE49K2
Note:
Comparator control register (CMPxCR)
Reset Value: 1000 0000 (80h)
Bit 7 = CHYST Comparator hysteresis enable
This bit is set or cleared by software and set by hardware reset. When this bit is set, the
comparator hysteresis is enabled.
To avoid spurious toggling of the output of the comparator due to noise on the voltage
reference, it is recommended to enable the hysteresis.
Bit 6 = Reserved, Must be kept cleared
Bit 5 = CINV Comparator output inversion select
This bit is set or cleared by software and cleared by hardware reset. When this bit is set, the
comparator output is inverted.
If interrupt enable bit CMPIE is set in the CMPCR register, the CINV bit is also used to select
which type of level transition on the comparator output will generate the interrupt. When this
bit is reset, interrupt will be generated at the rising edge of the comparator output change
(COMP signal, refer to
generated at the falling edge of comparator output change (COMP signal, refer to
on page
Bit 4 = CMPIF Comparator interrupt flag
This bit is set by hardware when interrupt is generated at the rising edge (CINV = 0) or
falling edge (CINV = 1) of comparator output. This bit is cleared by reading the CMPCR
register. Writing to this bit does not change the value.
Bit 3 : CMPIE Comparator interrupt enable
This bit is set or reset by software and cleared by hardware reset. This bit enables or
disables the interrupt generation depending on interrupt flag
CHYST
0: Hysteresis disabled
1: Hysteresis enabled
0: Comparator output not inverted and interrupt generated at the rising edge of COMP
1: Comparator output inverted and interrupt generated at the falling edge of COMP
0 : Comparator interrupt flag cleared
1 : Comparator interrupt flag set and can generate interrupt if CMPIE is set.
0: Interrupt not generated
1: Interrupt generated if interrupt flag is set
7
179).
0
Figure 82 on page
CINV
CMPIF
Read/write
179). When this bit is set, interrupt will be
CMPIE
CMP
On-chip peripherals
COUT
Figure 82
CMPON
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