ST7LITE49K2 STMicroelectronics, ST7LITE49K2 Datasheet - Page 95

• Manufacturer Part Number: ST7LITE49K2
• Description: 8-bit MCU
• Manufacturer: STMicroelectronics

Specifications of ST7LITE49K2

• 8 Kbytes Single Voltage Extended Flash (xflash) Program Memory With Read-out Protection In-circuit Programming And In-application Programming (icp And Iap) Endurance: 10K write/erase cycles guaranteed Data retention
• 256 Bytes Data Eeprom With Read-out Protection. 300k Write/erase Cycles Guaranteed, Data Retention: 20 years at 55 °C.
• Clock Sources: Internal trimmable 8 MHz RC oscillator, auto-wakeup internal low power - low frequency oscillator, crystal/ceramic resonator or external clock
• Five Power Saving Modes: Halt, Active-halt, Auto-wakeup from Halt, Wait and Slow

ST7LITE49K2
On-chip peripherals
One pulse mode
One pulse mode can be used to control PWM2/3 signal with an external LTIC pin. This
mode is available only in Dual Timer mode i.e. only for CNTR2, when the OP_EN bit in
PWM3CSR register is set.
One Pulse mode is activated by the external LTIC input. The active edge of the LTIC pin is
selected by the OPEDGE bit in the PWM3CSR register.
After getting the active edge of the LTIC pin, CNTR2 is reset (000h) and PWM3 is set to
high. CNTR2 starts counting from 000h, when it reaches the active DCR3 value then PWM3
goes low. Till this time, any further transitions on the LTIC signal will have no effect. If there
are LTIC transitions after CNTR2 reaches DCR3 value, CNTR2 is reset again and PWM3
goes high.
If there is no LTIC active edge, CNTR2 counts until it reaches the ATR2 value, then it is reset
again and PWM3 is set to high. The counter again starts counting from 000h, when it
reaches the active DCR3 value PWM3 goes low, the counter counts until it reaches ATR2, it
resets and PWM3 is set to high and so on.
The same operation applies for PWM2, but in this case the comparison is done on DCR2.
OP_EN and OPEDGE bits take effect on the fly and are not synchronized with Counter 2
overflow. The output bit OP2/3 can be used to inverse the polarity of PWM2/3 in one-pulse
mode. The update of these bits (OP2/3) is synchronized with the counter 2 overflow, they
will be updated if the TRAN2 bit is set.
The time taken from activation of LTIC input and CNTR2 reset is between 2 and 3 t
CNTR2
cycles, that is, from around 62.5 ns to 94 ns (at 32 MHz input frequency).
Lite timer Input Capture interrupt should be disabled while 12-bit ARtimer is in One Pulse
mode. This is to avoid spurious interrupts.
The priority of the various conditions for PWM3 is the following: Break > one-pulse mode
with active LTIC edge > Forced overflow by s/w > one-pulse mode without active LTIC edge
> normal PWM operation.
It is possible to update DCR2/3 and OP2/3 at the counter 2 reset, the update is
synchronized with the counter reset. This is managed by the overflow interrupt which is
generated if counter is reset either due to ATR match or active pulse at LTIC pin. DCR2/3
and OP2/3 update in one-pulse mode is performed dynamically using a software force
update. DCR3 update in this mode is not synchronized with any event. That may lead to a
longer next PWM3 cycle duration than expected just after the change.
In One Pulse mode ATR2 value must be greater than DCR2/3 value for PWM2/3. (opposite
to normal PWM mode).
If there is an active edge on the LTIC pin after the counter has reset due to an ATR2 match,
then the timer again gets reset and appears as modified Duty cycle depending on whether
the new DCR value is less than or more than the previous value.
The TRAN2 bit should be set along with the FORCE2 bit with the same instruction after a
write to the DCR register.
ATR2 value should be changed after an overflow in one pulse mode to avoid any irregular
PWM cycle.
When exiting from one pulse mode, the OP_EN bit in the PWM3CSR register should be
reset first and then the ENCNTR2 bit (if counter 2 must be stopped).
95/245